Encryption of source code modules by Gaoyun Yunyuan Software
Foreword:
In the actual development of [FPGA], the officially provided IP is not suitable for all situations and needs to be modified according to the actual situation. Or when we design the IP ourselves and need to call it again, we can encapsulate the previous design into a custom one. IP, and then continue to use this IP in subsequent designs.
Sometimes we want to share the IP files we designed with others, but we don’t want to share the source code with them. Then we need to encapsulate the source code into an IP model for others to call. Protecting one's own intellectual property rights promotes the sharing and progress of technology.
Therefore, this article will introduce in detail the use of Gaoyun's Yunyuan software to create IP and use IP to create projects.
one,
After designing your own project, you can encapsulate the hierarchical modules used in situ as needed.
It is introduced in Gaoyun software:
With the project open, when the user needs to edit all or part of the source files in the FPGA design
When encrypting source files, you can right-click the module to be encrypted in the Hierarchy window.
Generate the synthesized encrypted file through "Pack User Design" in the right-click menu. "Pack User
Design” dialog box as shown in the figure.
The meanings of each configuration in the Pack User Design dialog box are as follows:
Create In: The target path to generate the encrypted file. Only absolute paths are supported. The default is
Project path\src<topmodule_name>_pack;
Synthesis Tool: Specify the synthesis tool;
Language: Select the hardware language. The drop-down list supports Verilog and VHDL. It is selected by default.
Verilog；
Target Top Module: The top module that you want to encrypt. Defaults to in Hierarchy
The module selected in the window allows users to modify it;
Source Files: Lists the module selected in the Hierarchy window and its submodules.
source files;
Add File: Add the design file to be encrypted;
Remove File: Remove design files that do not need to be encrypted;
Output window: execution information window;
Pack: perform encryption;
Stop: Stop encryption.
two,
After encryption starts and the encryption is successful, relevant information will be printed in the Output window, as shown in Figure 3-5.
If there is error information during the encryption process, the error information will be displayed in the Output window, and at the same time
Print encryption failure information, as shown in Figure 3-6.
Figure 3-5 Pack User Design Dialog box print information
three,
After encryption is completed, two files will be generated in the target path. If Language is selected
Verilog, the generated files are <topmodule_name>_gowin.vp and
<topmodule_name>_sim.v, if the Language selected is VHDL, the generated file
The files are <topmodule_name>_gowin.vhdp and <topmodule_name>_sim.v.
<topmodule_name>_gowin.vp and <topmodule_name>_gowin.vhdp are for
Confidential encrypted files can be made available to others. <topmodule_name>_sim.v is a tie
The synthesized plaintext netlist file can be used for functional simulation of the encryption module.
Note!
If there are multiple modules in the project that instantiate the same sub module, pack these modules separately.
The definition of the sub module will be included in the files generated later. If these generated files are used in the same work
process, an error will be reported that the sub module is repeatedly defined. This usage needs to be avoided.