Article directory
- combinational logic circuit
- sequential logic circuit
combinational logic circuit
Analysis of Combinational Logic Circuits
- Combinational logic circuit: the current output is only related to the current input
Example 1 (three-variable majority voting machine)
- Description of the logical function:
We can see that among the three input variables, as long as more than two variables are 1, the result will be 1
---->The function is described as a three-variable majority voting device
Example 2 (XOR circuit of two variables) Improvement
- For the improvement of the circuit, the original function expression is not concise enough, resulting in the logic circuit diagram being too cumbersome. Therefore, after confirming the function of the circuit and drawing the Karnaugh diagram, further design of the circuit can be carried out based on the Karnaugh diagram.
Example 3 (full adder)
Design of combinational logic circuits
Example 1
Example 2 (encoding conversion 8421BCD into remainder 3 code)
Example 3 (Two-bit binary multiplier)
- How to understand a two-digit binary multiplier:
The multiplication of two binary digits by one digit does not bring about a carry, but when the last corresponding digits are added will bring a carry, so the final result must be stored in 4-bit binary
Example 4 (combined with real life)
Principles and applications of commonly used medium-scale combinational logic components
Half adder and full adder
简单来说，半加器就是没有考虑从低位的进位
全加器就是在半加器的基础上，增加了考虑低位的进位的作用
该图的第二个1000改成101
multi-bit binary addition
Applications of full adder
decoder
Binary decoder (converts decimal to binary) (74LS138 decoder)
Application 1
Application 2
Decimal decoder (convert binary to decimal)
Number picker
Application 1 (Implementing a three-variable majority voting machine)
How to use Karnaugh maps to make the most of number pickers
sequential logic circuit
Analysis of sequential circuits
Analysis of Synchronous Sequential Circuits
Example 1 (with input and output)
Example 2 (output only)
Let’s look at another example (no input, output)
The analysis steps are the same as the above example, the only difference is the truth table and state transition diagram
Example 3 (no input or output)
Analysis of Asynchronous Sequential Circuits
Example 1
summary
- To determine whether it is synchronous or asynchronous, directly look at the cp end of the trigger to see whether it is controlled by the same timing signal.
- Different circuits are generally the same, except that some circuits have inputs and outputs, so you should pay attention when writing truth tables, as well as excitation equations, characteristic equations, and output equations.
- If you want to draw a timing waveform diagram, you can draw a timing diagram first, or draw it directly based on the truth table.
- How to draw the migration diagram:
(1) Both input and output exist: state 1————(input/output)————state 2
(2) Only output: state 1————(/output)————state 2
(3) No input and output: state 1———— ——————State 2- For asynchronous sequential circuits: the status of the truth table should be judged according to the specific timing signal. Generally, if it is connected to cp, it will always be in the startup state. If it is not connected to cp, it must be judged whether it is a rising edge or a falling edge, 1 or 0.
对于异步还是对于同步的分析：最大的差别就是真值表上，同步电路是没有显示cp 端的，可是异步那里是会显示每一个触发器的cp 端口的
Design of sequential circuits
Design of synchronous sequential circuits
serial data detector
JK flip-flop design counter
- For the design of counters:
(1) Pay attention to what kind of flip-flop (JK or D) is required.
(2) Is it decrementing or incrementing? ? For example: design a modulo 5 counter: if it is decreasing, then 000 represents 5, and the next state after 000 is 100. Finally, 001 returns to 000; if it is increasing, then 000 is 0, and the next state is 001, and finally 100 Return to 000
(3) When migrating the truth table of the picture according to the state, the unused state should also be used. Use x to replace the state. This is the unknown state, which is convenient for drawing Kano later. Figure, but when later judging whether the counter has a self-starting function, it is necessary to write out the subsequent states of the unused state. If it can be connected to the original state transition diagram, it has self-starting capability, otherwise it will No
(4) Supplement (3): When analyzing the sequential circuit, since we don’t know what the modulo counter is, x is not used in the truth table, but Write the next state directly, so that you can draw a state transition diagram to directly determine whether it has self-starting capability
counter
Synchronous integrated counter 74LS161 (can carry out 4-bit binary counting)
- Explanation:
(1) For asynchronous clearing terminal Cr: When Cr is 0, it is cleared immediately and is not affected by CP
(2) Synchronous preset: When Cr = 1, LD = 0, at the rising edge of CP, the data of ABCD is sent to the counter (必须在CP作用下运行)
(3) The T and P terminals are always set to 1.
(4)Cr 与 LD 都是低电平有效，即在为0时工作
(5) Note that at the input terminal, A terminal is low and D is High bit, the same is true at the output end, Qa is low bit, Qd is high bit
- Expansion of 74LS 161 counter:
(1) For the asynchronous clearing terminal Cr: you can use the feedback clearing method to become an arbitrary base counter< a i=2> (2) For the synchronous preset terminal LD: the feedback preset method can be used to form an arbitrary counter (3)在对计数器的状态进行选择的时候，如果采用同步预置端进行反馈控制，那么一切正常，如果采用异步清零端进行反馈的时候，注意，要多加一个过渡态
Use multiple 74LS 161 to achieve counting greater than hexadecimal
- Notes:
(1) The A on the left is the lowest bit, and the D on the right is the highest bit. The counter on the left will generate an Oc output as the P of the counter on the right. The feedback signal controls two LD preset terminals, and the rest is no different from a single 74LS 161
Decimal reversible integrated counter 74LS 192
Binary reversible integrated counter 74LS169
Asynchronous integrated counter 74LS 90
Registers and shift registers
Serial transmission and parallel transmission
74LS 194 shift register
- Analysis:
(1) Cr is a direct clearing terminal, active low level
(2) SR is a right-shift serial data input terminal, SL is the left shift serial data input terminal
(3) CP is the pulse input terminal, rising edge action
(4) S1, S0 are working status S1S0 = 00 is the state maintenance, S1S0 = 01 is the right shift, S1S0 = 10 is the left shift, S1S0 = 11 is the parallel data transfer
Shift register constitutes shift counter
- Design process:
(1) Obtain the feedback function from the truth table (received to SR or SL)
f
Sequence signal generator
Combination of sequence signal generator and selector
Analyze state transition relationships and output sequences
- How to understand ?
(1) There is a falling edge pulse signal at the beginning of the Cr terminal, that is, the internal outputs of the 74LS 194 are all 0, because Q0 serves as D0, D1, and D2 of the four-select one selector. , assignment of D3, and Q1 and Q2 of 74LS 194 are used as inputs of the address of the selector, and a value of D0, D1, D2, D3 is selected as the output, that is, as a supplementary number for the left shift of the register
design
- For Karnaugh map to determine the combination of selectors:
(1) First confirm that Q1 and Q2 are the address variables of A1 and A0 of the selectors
(2) In the Karnaugh map, it is best to put Q2 and Q3 together. Taking the above example as an example, when Q2Q3 is 00, select D0, and so on, and then assign the value because it is Q1. It turns out that Q1 = 0, let D0, D1, and D3 all be 1. When it is 1, let D2 be 1
(3) Draw the logic diagram according to the design