Teach you how to learn FPGA by using Xilinx devices and EDA (vivado) - Baseline
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1. Baseline
Preface
Baseline can be regarded as one of the most in-depth properties of CSS`
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基础目标与策略
1. Describe the iterative method of incremental constrained design
Performance baseline is an iterative approach that adds timing constraints to the design, iterates through synthesis and implementation, and then performs static timing analysis to isolate the timing critical path. It has three stages.
(1) The primary focus is to identify internal device timing challenges early in the first phase of the process and apply All clock constraints and clock interactions.
Synthesize and implement designs, allowing Vivado Design Suite to focus on internal data paths between synchronized elements. The timing results become the performance baseline for the design.
(2) I/O constraints can be added and verified in the second phase.
Analyze the performance of the design against the performance baseline; when viewing the results, several I/O constraints are added.
(3) Path-specific constraints are added in the third stage, such as multi-cycle paths, false paths, and maximum delays.
a, FIFO is subject to its own path-specific constraints because it uses the IP catalog (IP editor);
b, false path constraints are introduced in the asynchronous reset design; < /span>
c. The synchronization register requires a maximum delay constraint to ensure that the signal reaches the next flip-flop (flip - flop).
2. Use the performance baseline process to obtain timing closure of the design
1. Progressive design timing closure
The recommended baseline closing strategy is a "progressive approach." It begins by synthesizing and implementing the design using simple clocking constraints. This allows the tool to focus on the internal data path, covering more than 90% of the latency paths in the design. This forms a performance baseline. Typically, this means that designers only need to establish a single clock constraint, but we also recommend that designers define each clock group as asynchronous during this iteration. This will prevent any timing issues from occurring on the paths between each individual clock in the design. Note that after completion of synthesis and implementation, STA and design analysis should be part of each step. Good design analysis techniques require identifying the bottlenecks or time-critical paths of the design and evaluating the number of LUTS inferred from the C or RTL code. After evaluating the timing critical paths, these failed paths should be fixed by modifying the code depending on whether the timing issue is in the clock path or the data path. Once the timing of the baseline clock constraints is closed, the next step is to perform the same process of adding I/O interface constraints, synthesis, and implementation. This step is separate from the first because I/O constraints are more complex and often not set properly. Finally, in the third phase of synthesis and implementation, timing exceptions and floor plan constraints can be added to help obtain timing closures and fine-tuning. Note that specific path constraints are typically used when the user has paths that appear to be timing critical, and these paths are multi-loop or require the wrong path constraints. This is also the time when designers typically ensure that their synchronization circuits are properly constrained. This may mean modifying earlier asynchronous clock group constraints based on the type of synchronous circuitry the designer needs.
2. Use TCL language to implement timing constraint Baseline in stages
Summarize
1. We recommend using a performance baseline process to incrementally constrain the design;
2. This incremental approach to achieving timing closure allows designers to avoid wasted software iterations and simplifies timing Verification of constraints.