ISE Design Suit 10.1 interface layout
1. Create a project
----> Click File > New Project... , fill in as shown in the pop-up dialog box
----> Click Next, fill in the figure in the pop-up dialog box
----> Click Next all the way, and finally click Finish
2. Create HDL source file---->Take Verilog as an example
---->Right-click the blank space in the project management area, and select New Source... in the pop-up shortcut menu.
----> Click Verilog Module in the pop-up dialog box, and the file name is written to counter, as shown in the figure
----> Fill in according to the figure below
----> Click Next all the way, and finally click Finish
----> The source file is as shown in the figure
----> Use code templates to complete the design
---->Click Edit → Language Templates... to pop up the Language Templates dialog box, click Window → Tile
Vertically to make the source file and template file visible at the same time, as shown in the figure
---->Click the "+" sign to find the following template Verilog → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
----> ClickEdit → Use in File or Use Template in File toolbar icon to copy the template to the source file, as shown in the figure
----> Edit the code file as shown below
module counter(input CLOCK; input DIRECTION; output [3:0] COUNT_OUT; ); reg [3:0] count_int = 0; always @(posedge CLOCK) if (DIRECTION) count_int <= count_int + 1; else count_int <= count_int - 1; assign COUNT_OUT = count_int; endmodule
----> Set as Implementation as shown
---->Select the source file, as shown in the figure
----> Expand Synthesize - XST and double-click Check Syntax, as shown in the figure
---->Simulation---->Select the HDL file as shown in the figure
----> Click Project → New Source and select Test Bench WaveForm and fill it out according to the picture
----> Click Next all the way, then click Finish
---->Set in the pop-up dialog box---->Clock frequency---->25MHz
---->Setup time---->10ns
---->Output delay time---->10ns
----> Set as shown and click Finish
----> The waveform diagram appears as shown in the figure, the blue shading represents the input setup time
---->Select Behavioral Simulation, as shown in the figure, you can view the simulation waveform file
----> As shown in the figure, double-click Simulate Behavioral Model to run the simulation
---->The simulation results are shown in the figure---->Verify whether the addition and subtraction functions are correct according to the waveform diagram
---->Create Timing Constraints---->Timing Constraints
----> Clock cycle constraints
----> Offset constraint
---->Select Implementation, select the source file counter, as shown in the figure
----> Double-click Create Timing Constraints as shown to generate a user constraint file (UCF)
----> A dialog box will pop up asking whether to add to the project, click Yes, counter.ucf will be added to the dialog box and automatically open the constraint editor
---->Fill as shown below
----> As shown in the figure, click Timing Constraints to view and save the constraint file
----> Execute the design ----> Select the counter source file, as shown in the figure
----> Double-click View Design Summary to view the design report, as shown in the figure
---->Double-click Implement Design as shown in the figure---->After successful execution, there will be a green check mark on it
---->Click All Constraints Met to view the timing constraints report, as shown in the figure
---->Specify pin assignment constraints---->Select the counter source file in the Source Window and double-click Floorplan Area/IO/Logic - Post Synthesis
to open the Xilinx Pinout and Area Constraints Editor dialog box, as shown in the figure
---->Select Package View as shown in the figure, and enter the pin name according to the figure
----> Save the file, select XST Default <>, and click OK
----> Re-execute the design and verify pin locations ----> Double click on View Design Summary
----> Select Pinout Report and select the Signal Name column to sort
----> Double-click Implement Design to re-execute the design
----> Double-click Pinout Report and select the Signal Name column to sort, the result is as shown in the figure
----> Download program