TLB (Translation Lookaside Buffer) is an important hardware unit that accelerates the translation of virtual addresses to physical addresses.
Due to the current mainstream multi-level page table structure, the MMU needs to access multiple page table entries during the process of translating virtual addresses. An address translation may result in multiple physical memory accesses. Therefore, a hardware unit TLB is introduced inside the MMU to accelerate this address translation process. Simply put, TLB can be simplified and understood as a hash table (mapping relationship) that caches key-value pairs of virtual page numbers and physical page numbers .
As shown in the figure below, the MMU will use the virtual page number as a key to query the cache entry in the TLB. If found, the corresponding physical page number can be obtained directly without further querying the page table operation. This process is a TLB hit. .
As shown internally in the figure below, usually the TLB hardware unit also adopts a divided architecture design. This can be compared with the hierarchical cache added during data transmission between the processor and the hard disk. It is divided into two layers: L1 and L2. L1 is subdivided into data TLB and instruction TLB. Address translation for cached data and instructions respectively. L2 does not distinguish between data and instructions; as a hardware unit inside the CPU, the TLB is very small, so the cache items are limited. Each CPU core typically has cache entries in the thousands.
Note: When the TLB misses, the hardware will query the page table through the page table base address to find the corresponding page table entry. Fill in the translation results into the TLB. If the TLB cache is full, it will be replaced.
