Source: Daisy Chain_Baidu Encyclopedia (baidu.com)
SPI daisy chain topology:
From: SPI daisy chain principle and configuration_Hao Big Fish’s Blog-CSDN Blog
Does SCK need to be of equal length, that is, does the signal from the master device to each slave device need to be processed with equal length? Dout->D between slave devices
Do the in wires also need to be of equal length?
I think it is necessary in theory. Different lengths of clock lines will cause skew in the clock and affect the signal collection effect. However, since the clock rate of SPI is usually not fast, compared with electrical signal propagation, this signal propagation delay can be ignored.
I saw DDR daisy chain mentioned on the Internet. At this time, it is necessary to consider the propagation delay and adopt equal length processing.