[RISC_V Course Notes] Introduction

Target

1. Completed the design based on CPU and three-level pipeline structure. Fetch (if), decode (id), execute (ex)
2. Design of cpu interrupt system
3. SOC design with CPU as the core, completes the design of rom, ram, time peripherals
4. Use uvm to verify the CPU (system verilog)

theory

digital logic circuit

Digital signal: A signal expressed in binary, that is, the signal is represented by 0 and 1.

digital encoding

The original code, complement code, and complement code remain unchanged when the number is positive. When expressing a negative number, for example: -1
original code: the sign bit is 1, other positions: 001 —> 1001
complement code: the sign bit remains unchanged, other positions are inverted: 110 —> 1110
complement code: based on the complement code + 1 —> 1111
Note : Computers store codes in two’s complement format.
Common codes: 2421BCD, 5421BCD, 8421BCD codes

2. CPU basic module

2.1 32-bit risc-v processor instruction format

• 0~6: Operation code opcode
• 7~11: Destination register rd
• 12~14: func3
• 15~19: rst1 source register 1
• 20~24: rst2 source register 2
• 25~31： func7

Assembly instruction example:

ADD rd, rs2, rs1

rst1寄存器的值 + rst2寄存器的值 ——> rd 寄存器的值