1.IMU
Model QMI8658C
IMU English data manual.
Refer to the connection and data manual for use.
Similar inertial navigation module development https://www.cnblogs.com/rockyching2009/p/15071669.htmlWeixue
https://www.waveshare.net/wiki/ RP2040-LCD-1.28
micro python: https://docs.micropython.org/en/latest/esp32/tutorial/intro.html
https://github.com/scottshambaugh/mpl_quaternion_views
1.I2C protocol
一般 I²C 芯片常用的传输格式有下列二种:
(Start)-[Control]-[Command]-[Data]-(End) (Start)-
[Control 0]-[Command]-(rStart)-[Control 1]-[Data]-( End)
I²C-Bus
consists of a single master (a microcontroller) and three slave nodes (an analog-to-digital converter), a digital-to-analog converter and another microcontroller), and uses the above Pull resistor Rp.
I²C uses only two bidirectional open drain lines, one of which is the serial data line (SDA) for transmitting data, and the other line is the serial clock (SCL) for starting or stopping transmission and sending clock sequences. lines, both lines have pull-up resistors [2]. I²C allows for a fairly wide operating voltage range, but typical voltage levels are +3.3V or +5v.
The i2c impedance is 50 and the USB impedance is 100. When doing signal conversion, the impedance mismatch will cause extremely poor signals.
Related information: wiki_I2C
IMU wiring under I2C protocol
usage pattern
According to the usage mode, if the IMU is only used as a slave device and not as the master device of the external magnetometer, the external sensor bus is disabled. At this time, it is Default Mode, that is, the following mode Mode 1: Default mode of operation. In this mode,
the QMI8658C is a slave device to a host processor that
communicates to it using one of the following interfaces: I2C, I3C, and SPI (3-wire or 4-wire modes). This slave
relationship to the host is the same for all operating modes . In Mode 1, the secondary interface is not enabled
O SDO/SA0 I2C Slave LSB bit of the device Address (SA0) ? There may be an internal pull-up resistor of 200kΩ here
IO SDx VDDIO or GND
IO SCx VDDIO or GND
O INT1 Programmable Interrupt 1 for I2C and SPI Programmable Interrupt 1
I VDDIO Power Supply for IO Pins IO pin power supply entrance 3.3V
I GND Ground (0 V supply); is internally No Connect.
I GND Ground (0 V supply)
I VDD Power supply power supply entrance 3.3V
O INT2 Programmable Interrupt 2( INT2)/ Data Enable (DEN) Programmable interrupt port 2 or data enable pin
I CS I2C/ I3C /SPI-UI selection Pin. Chip select pin chip select
(If 1: I2C-UI Mode: I2 C/I3C communication enabled, SPI idle mode)
(If 0: SPI-UI mode: I 2 C/I3C disabled)
IO SCL SPI-UI Serial Clock (SPC) (2)(3) SPI serial clock There are errors and omissions in the drawing text here
IO SDA I2C/I3C-UI Data (SDA) I2C data interface SPI four-wire mode Data In (SDI) SPI three-wire mode Data IO (SDIO)
2.SPI protocol
Special note: In SPI mode (not in I2 C Mode), there is an internal pull down 200 kΩ resistor. The
SCl port and SDA port have an internal pull down resistor of 200 kΩ in SPI mode
. Serial Peripheral Interface Bus (SPI)
IMU wiring under SPI protocol
usage pattern
According to the usage mode, if the IMU is only used as a slave device and not as the master device of the external magnetometer, the external sensor bus is disabled. At this time, it is Default Mode, that is, the following mode Mode 1: Default mode of operation. In this mode,
the QMI8658C is a slave device to a host processor that
communicates to it using one of the following interfaces: I2C, I3C, and SPI (3-wire or 4-wire modes). This slave
relationship to the host is the same for all operating modes . In Mode 1, the secondary interface is not enabled
O SDO/SA0 SPI-UI Data Out (SDO) in SPI-UI 4-Wire Mode. SPI data out port ? There may be an internal pull-up resistor of 200kΩ here
IO SDx VDDIO or GND
IO SCx VDDIO or GND
O INT1 Programmable Interrupt 1 for I2C and SPI Programmable Interrupt 1
I VDDIO Power Supply for IO Pins IO pin power supply entry 3.3V
I GND Ground (0 V supply); is internally No Connect.
I GND Ground (0 V supply)
I VDD Power supply Power supply entrance 3.3V
O INT2 Programmable Interrupt 2(INT2)/ Data Enable (DEN) Programmable Interrupt 2 or Data Enable Can pin
I CS I2C/ I3C /SPI-UI selection Pin. Chip select pin chip select
(If 1: I2C-UI Mode: I2 C/I3C communication enabled, SPI idle mode)
(If 0: SPI-UI mode: I 2 C/I3C disabled)
IO SCL SPI-UI Serial Clock (SPC) (2)(3) SPI serial clock SPI mode has internal pull-down resistor 200kΩ
IO SDA/SDI/SDIO SPI four-wire mode Data In (SDI) SPI three-wire mode Data IO (SDIO) SPI mode has an internal pull-down resistor 200kΩ
The SPI bus specifies 4 reserved logical signal interfaces:
SCLK（Serial Clock）：串列时脉，由主机发出
MOSI（Master Output, Slave Input）：主机输出从机输入信号（数据由主机发出）
MISO（Master Input, Slave Output）：主机输入从机输出信号（数据由从机发出）
SS（Slave Select）：片选信号，由主机发出，一般是低电位有效
SPI devices use full-duplex mode communication, which is a master-slave mode of a host and one or more slaves. The host is responsible for the initialization frame. This data transmission frame can be used for both reading and writing operations. The chip select line can select one from multiple slaves to respond to the host's request.
SPI is a de facto standard, which means that this specification has no corresponding technical standard. Therefore, the SPI devices produced by various manufacturers have different configurations and may not be interoperable.
Communication operations on the SPI bus can be performed between a single master device and one or more slave devices.
In the case of a single slave, the SS line can be fixed to a logic low if the slave allows it. However, some slaves require the falling edge of the chip select signal to trigger action. For example, the Maxim MAX1242 ADC will only start analog-to-digital conversion when it transitions from high to low. For multiple slaves, each slave requires an independent SS signal.
Most slave devices have tri-state logic characteristics, so when the device is not selected, their MISO signal becomes high impedance (logic open). Devices without tri-state outputs cannot share SPI bus segments with other devices, but an external tri-state logic cache can be used to solve this problem.
As shown in Figure 1, if the SS pin of a slave chip or slave device (slave) is in an inactive state (usually low level), then the slave chip or slave device is equivalent to a deaf person and will not respond to any external input. react to input signals. And if the SS pin of one of the slave chips is active, it can hear the external input signal and receive or respond. In Figure 1, MISO is the channel for transmitting data from the slave chip to the master chip, MOSI is the channel for transmitting data from the master chip to the slave chip, and SCLK is the clock channel (master chip -> slave chip).
advantage
The SPI protocol defaults to full-duplex communication.
As opposed to open-drain outputs, SPI's push-pull outputs provide good signal integrity and high speed
transmission bandwidth than I²C or SMBus. Not limited to any maximum clock frequency, enabling high-speed operation
shortcoming
Also requires more IC lines than I²C
and does not support dynamic addition of nodes (hot swapping).
没有从机检测机制，主机无法检测是否与从机断开。
没有错误检测机制，不像I²C在每个字节后有回复信号
没有规定中断，必须通过带外信号来实现中断，或者通过使用类似于USB 1.1和2.0的定期轮询来模拟中断
Related information: wiki_SPI
Waveshare IMU design: Related links
https://www.waveshare.net/w/upload/6/60/RP2040-LCD-1.28-sch.pdf