Verilog - blocking and non-blocking usage analysis

Blocking assignment and non-blocking assignment are always confusing. I have been programming in Verilog for a while, and now I finally feel clear about the specific rules of blocking and non-blocking assignment:

1. The assigned variable in the always block must be of type reg;
2. Statements similar to alwyas@(posedge clk) are used to describe sequential logic, and non-blocking assignment "<=" is used for assignment;
3. The always @(*) statement is used to describe complex combinational logic circuits, and blocking assignment "=" is used for assignment;
4. The assign statement can only describe combinational logic. The assigned variable is of wire type, and the blocking assignment "=" is used for assignment;

The meaning of blocking assignment and non-blocking assignment names:

• Blocking assignment means that multi-line assignment statements must be executed in order. The next line of statements can only be executed after the previous line of statements is executed, and the downward execution is "blocked".
• Non-blocking assignment means that when multiple lines of assignment statements meet the assignment conditions, they are executed simultaneously without "blocking"