[FPGA Project] Sandbox Exercise-Basic Version Message Sending and Receiving

                                        1st         virtual project

Preface

        Lighting up the lights has started our FPGA journey, so let's continue the sandbox exercise.

        Use a virtual project to get started with exercises to get your foot in the door of digital logic.

        Key Words: FIFO, SOF, EOF, counter, cache, timing diagram, solution design

1. Project requirements

1. The input message length is 64~2048 bytes;
2. The minimum interval between input messages is two beats;
3. Add 16-bit message length information to the first two beats of the output message; the first beat is the upper 8 bits of the message length; the second beat is the lower 8 bits of the message length; the third beat starts with the input message;

Signal	I/O	bit width	describe
System interface signal
i_sys_clk	I	1	System clock, 125Mhz
i_rst_n	I	1	Hard reset, active low
Input interface signal
i_sop_in	I	1	Input message header indication signal, high effective
i_eop_in	I	1	Input message tail indication signal, high effective
i_vld_in	I	1	Input message data valid signal, high valid
i_data_in	I	8	Enter message data
Output interface signal
o_sop_out	O	1	Output message header indication signal, high effective
o_eop_out	O	1	Output message tail indication signal, high effective
o_vld_out	O	1	Output message data valid signal, high valid
o_data_out	O	8	Output message data

Input interface timing

Output interface timing

2. Project plan design

2.1 Project requirements

1. Output message;
2. Output message length;
3. The message and message length output meet timing requirements;

2.2 Project plan

1. It is required to output a message, and the message output is after the message length is output, so the input message needs to be buffered first. According to the bit width and length range of the input message, the appropriate synchronization FIFO can be selected here; ( If it is an IC, then you need to write the FIFO yourself. You can refer to the FIFO introduction on this blog)

        The project here puts forward the first requirement, mastering the use of FIFO.

2. The length of the output message is required, so the length of the input message needs to be counted and cached;

        There is a pitfall here. If you only use a register to cache the length, there is a risk of being overwritten by the length of subsequent messages, so a second FIFO is needed to cache the length of the message.

3. It is required to output the message length first and then output the message. The timing needs to be designed here, the read and write timing of the FIFO needs to be mastered, and the clock edge sampling of the FPGA needs to be understood.

        Understanding: clock edge sampling and data changes on the next clock edge.

2.3 Project code

module zmj0001(
	input 			sys_clk,
	input 			rst_n,
	
	input			sop_in,
	input 			eop_in,
	input 			vld_in,
	input	[7:0]	data_in,
	
	output 			sop_out,
	output			eop_out,
	output			vld_out,
	output 	[7:0] 	data_out
	);

Of course, this is not the only design solution. You can consider the design and verification by yourself first.

If you need a complete code project, FPGA project sandbox drill-basic version message sending and receiving (vivado2017.4) resources-CSDN library

Major and difficult points of the project:

1. The use of FIFO and the design of timing
2. Consider packet interval 2 clk cycle
3. Consider the situation of long bag + ultra short bag

TimingDesigner software can be used for timing design. It is easy to use and can be downloaded if needed.

​​​​​​​3. Simulation Verification

Counters can be used to generate data sources data_in;

`timescale 1ns / 1ps

module zmj0001_tb();

reg					sys_clk				;
reg					rst_n				;
reg 	[7	:0]		data_in				;
reg					vld_in				;
reg					sop_in				;
reg					eop_in				;
reg		[11	:0]		cnt					;									
wire 				sop_out  			;
wire 				eop_out             ;
wire				vld_out             ;
wire 	[7:0] 		data_out            ;

initial
begin
	sys_clk		=	0;
	rst_n		=	0;
	#100
	rst_n		=	1;
end
always #5	sys_clk	=	~sys_clk;	//100Mhz
//用计数器来产生data_in
always @(posedge	sys_clk	or	negedge	rst_n)begin
	if(~rst_n)
		cnt				<=		12'b0;
	else if(cnt > 2048)
		cnt				<=		cnt;
	else
		cnt				<=		cnt	+	12'b1;
end
always @(posedge	sys_clk	or	negedge	rst_n)begin
	if(~rst_n)begin
		data_in			<=		8'b0;
		sop_in			<=		1'b0;
		eop_in			<=		1'b0;
		vld_in			<=		1'b0;
		end
	else begin
		data_in			<=		8'b0;
		sop_in			<=		1'b0;
		eop_in			<=		1'b0;
		vld_in			<=		1'b0;
		if((cnt > 'd10  &&   cnt  <=  'd60)|(cnt > 'd68  &&   cnt  <=  'd668))begin
			data_in		<=		data_in + 1'b1;
			vld_in		<=		1'b1;
			end
		if((cnt == 'd11)|(cnt == 'd69))
			sop_in		<=		1'b1;
		if((cnt == 'd60)|(cnt == 'd668))
			eop_in		<=		1'b1;
		if((cnt == 'd62) | (cnt == 'd63))begin  //63  66
			data_in		<=		data_in + 1'b1;
			vld_in		<=		1'b1;
			sop_in 		<= 		1'b1;
			eop_in 		<= 		1'b1;
			end
		
		end
end	


zmj0001		u_zmj0001(
	.sys_clk			(sys_clk   ),	
	.rst_n              (rst_n     ),
						 			
	.sop_in             (sop_in    ),
	.eop_in             (eop_in    ),
	.vld_in             (vld_in    ),
	.data_in            (data_in   ),
						 			
	.sop_out            (sop_out   ),
	.eop_out            (eop_out   ),
	.vld_out            (vld_out   ),
	.data_out           (data_out  )
	);

endmodule

        For the specific use of modelsim and joint simulation with vivado, please refer to other blog posts for script writing. We will consider writing related content in other FPGA columns in the future.

        Focus on edge cases when validating .

enter:

        A total of 4 packets of data, long packet + ultra short packet + ultra short packet + long packet, the packet interval is 2clk cycle

        data_in: The first package: the cumulative number of 1-50; the second package: 1; the third package: 1;

Output:

What if the packet interval is <2 clk?

enter:

Output:

As you can see, this design even supports back-to-back ultra-short packet input.

4. Project Harvest

1. The importance of scheme design: Any project starts with scheme design. It takes a lot of effort to clarify the ideas in the early stage. After the scheme design is completed, the code implementation is just a matter of course.
2. Learning from simulation: Through this project, the writing of testbench and simulation verification are completed. It is a test of your own design and the best tool to shorten the debugging time of actual projects.
3. Use xilinx IP and read and study datasheets.
4. To understand timing, the clock is the heartbeat of the FPGA: any timing operation occurs on the transition edge of the clock. When sampling occurs at the current rising edge moment, data changes occur at the rising edge of the next moment.
5. Draw timing diagram, use of TimingDesigner. With the sequence diagram, the code is easy to implement.

5. Advanced Considerations

This virtual project aims to use the simplest examples to help everyone understand some basic concepts of digital logic design, so many things are not considered. for example:

1. What if the packet interval is less than 2 clock cycles? -----Handshake and back pressure
2. What if there are errors in the input data? -----CRC check
3. What if transmission across clock domains is required? -----CDC processing
4. The message is simply forwarded. What if it needs to be processed? -----data processing
5. ...

Therefore, the next article will follow this idea. The advanced version of the virtual project can also be used as the company’s onboarding training.

See you next time!