AHB, APB and ASB belong to the AMBA bus architecture specification, which was proposed by ARM.
Table of contents
3. AHB master-slave communication process
1. AHB bus
AHB (Advanced High Performance Bus) means advanced high-performance bus, which can connect various controllers with AHB interfaces such as microcontrollers (CPUs), high-bandwidth external memory interfaces, high-bandwidth on-chip RAM, and DMA buses. , forming a complete SOC system. APB can be connected through the AHB-APB bridge.
APB (Advanced Peripheral Bus), which means advanced peripheral bus, can also be subdivided into APB1 and APB2 in STM32
- APB1 is responsible for DA, USB, SPI, I2C, CAN, TIM, and serial port 2345, mainly supporting work in low-speed conditions .
- APB2 is responsible for AD, I/O, advanced TIM, and serial port 1. Mainly, APB2 supports high-speed work.
2. AHB bus composition
The AHB bus can connect DMA, high-speed RAM, high-speed memory and other controllers with AHB interfaces. These controllers/hardware devices can be roughly divided into four categories.
- AHB master device: The bus master can initiate a read/write operation through address and control information. Only one master occupies the bus at a time
- AHB slave: The bus slave responds to read and write operations initiated by the master. The bus slave will feed back the signal of read and write success or failure to the master device
- AHB arbiter: When multiple devices apply to occupy the bus, arbitration will be initiated to ensure that only one device occupies the bus at a time
- AHB decoder: used to decode the address of each transfer and include a slave device selection signal in the transfer
In order to facilitate the address and data transmission of master/slave devices, each master/slave device will be connected to three buses
- HADDR : address control bus
- HWDATA : Write data bus ( for data transfer from Master to Slave )
- HRDATA: Read data bus ( for data transfer from Slave to Master )
3. AHB master-slave communication process
Select primary device
The Master that needs to occupy the bus sends a request to the arbiter, and the puncher authorizes the designated Master. Only one Master can occupy the bus at any time, and the Master occupying the bus can perform read and write operations on its designated Slave.
Select slave device
Master sends out address and control signals, providing address information, transmission direction, bandwidth and brust type. The decoder determines which Slave communicates with the Master according to the address and control signal.
- Address cycle: Transport address. Take one cycle
- Control cycle: transfer read and write direction. Take one cycle
- Data cycle: transmit data. Takes one or more cycles (the number of cycles is controlled by the HREADY signal)
data transmission
Under normal circumstances, only when the Master completes a complete data transmission, the blanker will authorize other Masters to access the bus. Sometimes, in order to avoid excessive decision delay, the blanker may also interrupt the burst transmission. In this case the Master must access the bus again for the remainder of the transmission.
Reference article:
FPGA Nexter - Introduction to AMBA (AHB) bus and interface definition - Zhihu (zhihu.com)
AHB bus protocol (1) - Mike Wolf 2012 - Blog Park (cnblogs.com)
AMBA bus - detailed explanation of AHB bus protocol - qq_28541715's blog - CSDN blog