- ATPG automatic test pattern generation
1. physical defects
-
short and open
-
drc escape
Features such as diversity
It is not easy to test, so the academic community has proposed the concept of fault model, and its specific functions are test generation fault simulation
quality prediction fault diagnosis
In addition to testing, it can also specifically analyze the coverage of the chip
fault model definition: describe the behavior of errors
2. Types of fault models
stcuk at fault model Note that it has nothing to do with technology
The second type is dealy fault model
Behavior representation: for example, 100M can work, 600M can’t work
The delay fault model is divided into two transition delay fault models
path delay fault model
transition delay faults ：slow to rise slow to fall
path delay fault: In fact, the transition delay can be regarded as a special path delay
Describe this fault is that the delay of the entire path is greater than the clock cycle
In fact, this kind of fault model is closer to the actual situation, but why not use this kind of model, because there are too many paths on the path, a good model can not only reflect the specific defect characteristics, but also be easy to solve. Obviously, the path delay fault model does not have the second 2 characteristics
IDDQ fault moel rarely used
That is, when the transistor is not working, the leakage current is too large, but now that the size is small, the leakage current itself is relatively large, and this threshold is not easy to set.
Therefore, most of the fault models used now are stuck at and transition delay fault models, and these two models are solved to generate structural test vectors
3. collapsing faults list
Of course we hope to do a complete test exhaustive testing, but in fact it is impossible, too waste of time
For an AND gate, an input stuck at 0 is equivalent to an output stuck at 0,
-
(1) Fault free normal output If the vector detect to fault, then it will be different from the fault free ciruit circuit
-
(2) Can be considered equivalent by the same vector detect to fault
-
(3) For equivalent faults, they are divided into one category, and one category can generate a structural test vector
Suppose the fault free circuit is represented by h(x)
faulty circuit 用 hu(x)
It can be clearly concluded that: Two XORs get 1
Example: a stuclk at 1 to solve ab=01
Example: significantly fewer test vectors after fault collasping
4. atpg tcl and results
5. atpg flow
The generated structural test vectors are all based on the fault model
Select the fault model and solve it based on the D algorithm
6. What is the D algorithm
ATPG general rules
some jargon
Example: If the first AND gate wants to forward D, then the other port must be 1 or d
If the 1 output by the second AND gate is to be sent to backward, then the input must be 1
7. fault simlution
Two parallel fault simulations
parallet pattern single fault propagation
References
Original link: https://blog.csdn.net/gaiyi8666/article/details/80867362