[C language] Embedded C language project management tool: in-depth understanding of the application and practice of Makefile

Table of contents

1. Overview of makedile

1. Case introduction

2、makefile 

3. Advantages of Makefile

2. Grammatical rules of makefile 

1. Grammatical rules

2. Simple combat

Three, makefile variables

1. Custom variables

2. System environment variables

3. Predefined variables

4. Advanced makefile

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1. Overview of makefile

1. Case introduction

gcc a.c b.c c.c ‐o main

If only bc is modified and compiled with gcc, all files need to be recompiled. makefile avoids this problem.

2、makefile 

make is a command , an executable program, which is used to parse the commands of Makefile files .

makefile is a file that describes the compilation rules of the program .

3. Advantages of Makefile

        (1) Simplify the commands entered when compiling the program. When compiling, you only need to type the make command.

        (2) It can save the second compilation time and improve the compilation efficiency

2. Grammatical rules of makefile 

1. Grammatical rules

Target file name: dependent file (establish relationship)

<Tab> command list

Target file: the file that needs to be generated (executable file, other obj file or action name)

Dependent files: Generate target files from dependent files (usually there are several dependent files)

Command list: the implementation will rely on the file to generate the target file (when there are multiple commands, each command occupies one line)

Take gcc ac bc cc -o main to compile three files as an example:

Grammar example:

main:a.c b.c c.c

        gcc a.c b.c c.c ‐o main

2. Simple combat

(1) Create and write test.c file

#include <stdio.h>
int main(int argc, char const *argv[])
{
    printf("hello world\n");
    return 0;
}

(2) Create and write makefile

main:test.c
    gcc test.c ‐o main

(3) Finally, enter the command make in the linux terminal to compile the test.c file

By default, make looks for files named GNUmakefile, makefile, and Makefile in the working directory as input files

make -f custom makefle filename takes the file with custom filename as input file

make will implement the first target in the makefile by default . make target file name -----> select target execution .

When there are multiple targets, the command make target file name: another target file name -----> select multiple targets to execute .

3. Complicated actual combat

(1) Create and write fun.c

int my_add(int x, int y)
{
    return x+y;
}
int my_sub(int x, int y)
{
    return x-y;
}
int my_mul(int x, int y)
{
    return x*y;
}
int my_div(int x, int y)
{
    return x/y;
}

(2) Create and write fun.h

#ifndef __FUN_H__
#define __FUN_H__

extern int my_add(int x, int y);
extern int my_sub(int x, int y);
extern int my_mul(int x, int y);
extern int my_div(int x, int y);

#endif

(2) Create and write main.c

#include <stdio.h>
#include "fun.h"
int main(int argc, char const *argv[])
{
    printf("%d\n", my_add(10, 20));
    printf("%d\n", my_sub(10, 20));
    printf("%d\n", my_mul(10, 20));
    printf("%d\n", my_div(10, 20));

    return 0;
}

(3) Create and write makefile

main:main.o fun.o
    gcc main.o fun.o -o main
main.o:main.c
    gcc -c main.c -o main.o
fun.o:fun.c
    gcc -c fun.c -o fun.o
clean:
    rm *.o main

Program flow: When main.o and fun.o are not found when the first target is to be executed, it will look down for the instructions to generate main.o and fun.o, and only after executing the instructions to generate main.o and fun.o Return to execute the first command.

Problem: When there are too many .o, the corresponding instructions will increase, you can use the variable optimization of makefile

Three, makefile variables

1. Custom variables

Makefile variables are similar to macros in C language . Variable names can start with numbers and are case-sensitive . They are generally defined at the head .

variable name = variable value

Get variable value: $(variable name) or ${variable s

Take the more complicated actual combat in the second middle school as an example to make custom modifications:

//自定义变量
cc=gcc
exec=main
obj=main.o fun.o

//用自定义变量做部分修改
$(exec):$(obj)
$(cc) $(obj) ‐o $(exec)
main.o:main.c
$(cc) ‐c main.c ‐o main.o
fun.o:fun.c
$(cc) ‐c fun.c ‐o fun.o
clean:
rm *.o $(exec)

2. System environment variables

Before the make tool parses the makefile, it reads the system environment variables and sets them as the variables of the makefile.

View environment variable command under linux : env

Command to add system environment variables under linux : export variable name to be added = variable value , for example: export cc=gcc.

3. Predefined variables

4. Advanced makefile

Take the more complicated actual combat in Optimization II as an example:

//自定义变量
cc=gcc
exec=main
obj=main.o fun.o
flags=‐Wall
//用自定义变量和预定义变量修改优化
$(exec):$(obj)
    $(cc) $^ ‐o $@ $(flags)
%.o:%.c//此时只需一条语句即可完成多条编译语句
    $(cc) ‐c $< ‐o $@ $(flags)

clean:
    rm $(obj) $(exec)