Spyglass CDC inspection one

Transfer: https://blog.csdn.net/zhong_ethan/article/details/106708346?spm=1001.2014.3001.5502

Article directory

This article is the first article in the SPYGLASS CDC inspection series. For the sake of simplicity, the operations in this article are basically carried out in GUI mode.

Familiar with the interface

Enter spyglass -project test.prj in Terminal & create or open a spyglass project.
The top of the GUI interface is the toolbar,

Click help to view the spyglass manual. Looking at the spyglass manual is the best way to learn spyglass.
Click Design setup to enter the interface for reading in the design
Click Goal Setup to enter the goal selection interface
Click Analysis results to view the inspection results

(1) Read in the design

The following documents are required

RTL code / Flist
SGDC Constraints Document
lib library//If there are library units in the design module, such as SRAM, clock gating, etc. (1) provide lib; (2) or provide the RTL file of the library unit, and set the library unit as BlackBox
Waiver file //The file for filtering the inspection results, not necessary, try not to use it.
In the process of set_option , set the top layer of the module (required), blackbox, search path and other parameters.

(2) Select the inspection target
spyglass is very powerful, it can do code inspection, CDC inspection, power consumption inspection, etc. This article only covers CDC inspections.
insert image description here (3) Analysis and inspection results
Be sure to check each result. If an error is reported, first check the cause of the error in the leftmost help viewer. If it is an RTL code problem, optimize the code. If it is determined that there is no problem, modify the constraint script and increase constraints until each item is green.
insert image description here

constraints file

Constraint files are prepared before being read into the design step, and can also be refined during the review process. The most basic constraints include clock, reset, input, and output port constraints.

//指定模块顶层
current_design training 
//约束时钟, 模块顶层所有的时钟都要约束
clock -name CLKA -period 10 -edge {
    
    0 5}
clock -name CLKB -period 100 -edge {
    
    0 50}
//约束复位
reset -name reset_a -value 0
reset -name reset_b -value 0
//约束输入端口
input -name {
    
    in_a in_b reset_a} -clock CLKA
input -name {
    
    resetn_b} -clock CLKB
//约束输出端口
output -name {
    
    dout} -clock CLKB
//如果有SDC约束文件
sdc_data -file ../my_file.sdc

Both the clock and generated_clock commands can constrain the clock.

clock Constrains the clock pin of the module port input.
generated_clock constrains the clock generated by the internal timing logic of the module , such as a frequency divider. Similar to create_generated_clock in SDC.

CDC process

Goal : It is a collection of related Rules, combined to complete a specific task of RTL analysis.
Rule: It is the smallest unit of SpyGlass for RTL analysis.

The cdc_setup and cdc_setup_check processes mainly check whether the constraint file is complete. Make sure that all input and output ports are 100% bound.
The cdc_verify_struct process mainly checks whether the signal is synchronized
The cdc_verify process mainly checks data loss, aggregation problems, and handshakes identified by the report, FIFO module

cdc/cdc_setup-> CDC check of Spyglass (2)
cdc/cdc_setup_check-> CDC check of Spyglass (3)
cdc/verify_struct (structural cdc checks )-> CDC check of Spyglass (4)
cdc/verify (functional cdc checks)-> CDC check of Spyglass (5)