Spyglass CDC inspection three

Transfer: https://blog.csdn.net/zhong_ethan/article/details/106841986?spm=1001.2014.3001.5502

This article mainly introduces the second process CDC_setup_check of CDC inspection, including Clock_info03a, Clock_info05a/b and Clock_info18 inspection items

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Clock_info03a

Report the unconstrained clock pins in the design, and the following situations will report violations.

• The clock is disabled after combinatorial logic
  
• There are no constraint clock pins in the constraint file, and the use_inferred_clocks parameter is set to No
  
• There is a Blackbox on the clock path, and the clock output by the Blackbox is not constrained
  
• Clocks are not transmitted in the design
  

Clock_info05a/b

If there are multiple clocks passing through the selector in the design, it needs to be constrained by the set_case_analysis command.

In the above example, there are two input clocks, clk1 and clk2, and one clock is output after passing through the selector. If the selector is not constrained, a violation will be reported, and the constraint file can be modified to:

clock -name clk1
clock -name clk2
set_case_analysis -name sel1 -value 0
set_case_analysis -name sel0 -value 0

Clock_info18

Reports unconstrained pins in the design.
The following pins must be constrained in the constraint file: input pins (including clock, reset signal), output pins and BLACKBOX pins.

• For top-level input and output pins, the following commands can be used in the constraint file: input, output, clock, reset, set_case_analysis, abstract_port.
• The pins of BLACKBOX can be constrained by the following commands: clock, reset, abstract_port, assume_path and signal_in_domain.
  How to use the above commands, you can refer to the spyglass help documentation to read carefully.