Compiling the driver generally uses compiling the driver into a module (.ko file), and then loading it into the kernel, which uses the make modules command.
Table of contents
1. Compile a c file into a ko file
2. Compile multiple files into one ko file
2. Multi-module compilation (multi-file and multi-module)
1. Single module compilation
1. Compile a c file into a ko file
The following is the simplest single-file single-module compilation. Suppose we want to compile the source file chrdevbase.c into a ko file.
KERNEL_DIR := /home/pigeon/workspace/imx6ull-kernel/linux-imx-rel_imx_4.1.15_2.1.0_ga_alientek
CURRENR_DIR := $(shell pwd)
obj-m := chrdevbase.o
build: kernel_modules
kernel_modules:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) modules
.PHONY:clean
clean:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) cleanKERNEL_DIR := xxx
KERNEL_DIR represents the location of the kernel source code, which will be used in subsequent make modules
CURRENR_DIR := xxx
CURRENR_DIR represents the path where the current module source file is located
obj-m := chrdevbase.o
obj-m means to compile the file chrdevbase.o as a "module", which will not be compiled into the kernel, but will generate an independent ko file
obj-y is directly compiled into the kernel, that is, added to the kernel source code
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) modules
We split this sentence into two stages, from simple to complex analysis. -C $(KERNEL_DIR) means to switch the working directory, because the top-level Makefile of the kernel source code defines pseudo-target modules, so the working directory must be switched to the location of the top-level Makefile of the kernel source code.
make modules -C $(KERNEL_DIR)M=$(CURRENR_DIR) means return to the current path and continue to execute the current Makefile. This allows the makefile to return to the specified directory to find the source code of the module, compile it, and generate a ko file.
make modules -C $(KERNEL_DIR) M=$(CURRENR_DIR)2. Compile multiple files into one ko file
Suppose we want to compile add.c and sub.c into a ko file, only add.c contains the module initialization function (module_init), and sub.c is only a dependent source file of add.c. It is roughly similar to the above single-file single-module, the differences are as follows:
- obj-m += modulename.o
- module-name-objs += source-file-name.o ...
like:
- obj-m +=: calc.o
- calc -objs += add.o sub.o
KERNEL_DIR := /home/pigeon/workspace/imx6ull-kernel/linux-imx-rel_imx_4.1.15_2.1.0_ga_alientek
CURRENR_DIR := $(shell pwd)
obj-m += calc.o # obj-m += 模块名.o
calc-objs := add.o sub.o # 模块名-objs += 源文件名.o ...
build: kernel_modules
kernel_modules:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) modules
.PHONY:clean
clean:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) clean2. Multi-module compilation (multi-file and multi-module)
From the above "Multi-file Single Module", we can understand that obj-m specifies the final module name, and <modules_name>-objs specifies the list of dependent source files. So if you want to generate multiple modules, you need to specify it through obj-m, and the final module name should correspond to the source file name.
KERNEL_DIR := /home/pigeon/workspace/imx6ull-kernel/linux-imx-rel_imx_4.1.15_2.1.0_ga_alientek
CURRENR_DIR := $(shell pwd)
obj-m += hello.o calculate.o # 需要存在对应的 hello.c 和 calculate.c 文件
build: kernel_modules
kernel_modules:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) modules
.PHONY:clean
clean:
$(MAKE) -C $(KERNEL_DIR) M=$(CURRENR_DIR) clean