I was thinking of updating the IAP remote upgrade (3) on Saturday, but on Wednesday, the unit suddenly informed the team to climb the Great Wall on Saturday, and I was exhausted when I came back at night. I turned on the computer and opened NetEase Cloud Music. I was lying in bed for a while, but I woke up at three o'clock at night, so I adjusted it and started writing this blog on Sunday night. The brain-wrenching concepts and logic are clearly organized and restored to readers.
The first two blogs of IAP remote upgrade introduced the background knowledge and working principle of IAP upgrade in detail, so this blog will directly go straight to the point, that is, how to realize IAP upgrade. In this blog, the author will take you step by step with the STM32CubeMX launched by ST , Configure the stm32f103rct6 initialization settings of the pea development board through a graphical interface . Here we only use a serial port of the single-chip microcomputer, and use DMA + idle interrupt to receive messages from the PC- side host computer.
As shown in Figure 1 , the internal clock tree setting of stm32f103rct6 suddenly looks very complicated. In fact, the essence is to multiply the external 8Mhz clock to a 72Mhz system clock through the internal PLL phase-locked loop . Of course, there are some concepts such as HSE ( High-speed external clock) source is external crystal oscillator speed 8Mhz ; PLLCLK (phase-locked loop clock) source is HSI or HSE after frequency multiplication , HCLK ( AHB high-speed bus clock): source is obtained by system clock frequency division, the speed is up to 72M by CFGR HPRE control; PCLK1 ( APB1 low bus clock): the source is HCLK frequency division, the speed is up to 36M to provide clocks for peripherals on the APB1 bus by the RCC_CFGR clock configuration registerPPRE1 bit control; PCLK2 ( APB2 high bus clock): the source is HCLK frequency division, the speed is up to 72M , and the clock provided for the peripherals on the APB2 bus is controlled by the PPRE2 bit of the RCC_CFGR clock configuration register .
Figure 1 Internal clock tree of stm32f103rct6
As shown in Figure 2 is the hardware schematic diagram of the pea development board stm32f103rct6 , as shown in Figure 3 is the crystal oscillator clock and UART1 pins of the stm32f103rct6 configured under STM32CubeMX , here we can do a good job of pin matching on the hardware, of course STM32CubeMX is also very User-friendly options are given, and users can also see the different definitions supported by each pin when configuring the graphical interface.
Figure 2 The crystal oscillator clock and serial port 1 circuit diagram of the pea development board stm32f103rct6
Figure 3 STM32CubeMX configures the crystal oscillator clock and UART1 pin of stm32f103rct6
As shown in Figure 4 , the debugging method of configuring stm32f103rct6 under STM32CubeMX is JTAG (5 pins) . It should be noted that it needs to be checked here, otherwise the generated code does not support JLINK or STLINK downloader online simulation debugging.
Figure 4 STM32CubeMX configuration stm32f103rct6 debugging method
As shown in Figure 5 , the system configuration of UART1 under STM32CubeMX mainly configures three key points: 1. Serial port baud rate and bit width; 2. Serial port DMA channel; 3. Serial port pin definition.
Figure 5 STM32CubeMX configures UART1 of stm32f103rct6
As shown in Figure 6 , STM32CubeMX configures the HAL library version of the initialization project of stm32f103rct6 . Here we select the MDK-ARM V5 version, which is the version supported by KEIL , select the latest HAL library version, and click GENERATE CODE directly to generate the initialization code. As shown in Figure 7 , it is the stm32f103rct6 initialization project generated under STM32CubeMX .
Figure 6 STM32CubeMX configuration stm32f103rct6 initialization project HAL library version
Figure 7 The stm32f103rct6 initialization project generated under STM32CubeMX