[cadence virtuoso practice record (2)_Manual calculation and design of 5 tubes_OTA (active load differential pair)]
1 parameter index
Process SMIC0.18um
working voltage VDD = 2.5V
slew rate SR ≥ 20V/us
load capacitance C_L = 2 pF
3dB bandwidth f 3 d B f_{3dB}f3 d B≥ 1MHz
DC Gain |Av| ≥ 40
Power Consumption P ≤ 0.5mW
Common Mode Voltage V_{ICMR} = [ 0.8V , 1.6V ]
2 calculation process
See the handwritten version for detailed process
3 simulation process
3.1 Build the schematic diagram according to the W/L calculated in 2
3.2 Simulation results
3.2.1 dc simulation
1. Set the VCM and VB values calculated in 2.
Run the DC simulation to check the working status of the tube.
2. At the beginning, I forgot to set the W/L of the tailpipe. Press 220/180 to run, the pipe works in the linear area, increase the VB to 1.5v until it is saturated, and find the problem after inspection, adjust the W/L of the pipe, and then set the VB to 0.59V, then it can work normally.
3. The adjustment of the static working point of the pipe has not been fully grasped, and the understanding of this area needs to be strengthened.
3.2.2 ac simulation
1. Add a small AC signal with an amplitude of 0.2V to the input,
set the output, click Run, and check the gain and phase
Figure↓testbench
Figure ↓ The gain is 82.7
, which meets the requirements of the index and is greater than 40 times.
Display the gain as dB.
Note here that because the input is mv, directly use the dB20 function to calculate the gain, and a negative value will appear,
20lg(0.0827V) = -21.64dB
Here we set the expression for gain_dB, divide the output by the input, and click dB20.
The result is displayed as 38.353dB
Gain-phase simulation results
3.2.3 3dB bandwidth
According to the results of the data simulation in 2, check the 3dB bandwidth.
f -3dB =1.18M
can also be viewed with the bandwidth function in the calculator
To increase the 3dB bandwidth, according to the formula
f 3dB = 1 R out CL \frac {1}{R_{out}C_{L}}RoutCL1
R o u t R_{out} Rout = V E L I D \frac {V_{E} L}{I_{D}} IDVEL
Then, reduce R out R_{out}Rout→ Reduce load tube L
Get f 3dB = 1.82MHz
3.2.4 Slew rate
1. Replace vdc with vpulse, under voltage setting
2. Set the transient simulation window
3. Set the output SR
The simulation result shows that SR has only 0.776V/μs
which does not meet the design requirement.
Improve:
Records:
1. The records are messy, and I haven't had time to sort them out
To be continued. . . .