Table of contents
introduce
Looking back at the development history of interface technology, in fact, the data transmission started with a low-speed serial interface (Serial Interface, referred to as serial port). In order to increase the total bandwidth of data, the first thing that comes to mind is to increase the data transmission bit width, and then further increase the rate. That is, the way of parallel interface (Parallel Interface, referred to as parallel port), and gradually replace the traditional low-speed serial port to become the mainstream. But with the development of the parallel port, its limitations are becoming more and more obvious. The advantages of high-speed serial (High Speed Serial, HSS) interface technology make it a trend to replace the current parallel port. This is manifested as a significant increase in the total bandwidth of the interface. Its history is like upgrading from mountain trails to country roads, and then to highways (networks), which can provide higher traffic volumes.
At present, the development of parallel ports is mainly limited by the fact that on the one hand, the chip package is facing the problem of a tight number of IOs; on the other hand, the problems of crosstalk (Crosstalk) and noise (SSN) faced by the parallel port in the process of increasing the data rate make data synchronization difficult.
1. Serdes (concept-process)
1. Concept
SERDES, or Serializer / Deserializer, is the abbreviation of serializer and deserializer, and is a technology widely used in high-speed serial data transmission. It serializes parallel data into a high-speed serial data stream and restores the sequence to original parallel data at the receiving end.
SERDES technology is usually used in point-to-point transmission scenarios, such as between chips, between boards or between chassis, because these scenarios require the transmission of large amounts of data, long distances and high speeds. SERDES technology can provide high-speed, reliable data transmission by reducing the number of lines and reducing the length of lines.
SERDES technology usually consists of two parts: serializer and deserializer. The serializer is used to convert the internal parallel data sequence into a high-speed serial data stream, and the deserializer converts the received high-speed serial data stream back to the original parallel data sequence. In SERDES technology, clock recovery circuits and synchronization circuits are also included to ensure correct recovery of data.
SERDES technology is widely used in modern communication, network, storage and other fields, such as PCI Express, SATA, USB3.0 and other standards all adopt SERDES technology to provide high-speed and reliable data transmission.
2. Technical status
SERDES technology is widely used in modern communication, networking and storage systems. With the popularity of data centers and cloud computing, the demand for high-speed serial interfaces is increasing, so SERDES technology is becoming more and more important in these fields.
In recent years, SERDES has been further developed in the following ways:
Higher data transmission rate: SERDES technology has been able to provide 10 Gbps or even higher data transmission rate. For example, PCIe 4.0 and 5.0 standards adopt a rate of 16 GT/s, enabling high-performance computing and data center applications to obtain better performance and response speed.
Lower power consumption and cost: With the advancement of technology and the improvement of integration, the power consumption and cost of devices are gradually reduced. For example, SERDES IP cores in modern FPGAs are already capable of data transfers in excess of gigabits per second (Gbps) at low power consumption and high bandwidth.
Higher reliability and anti-interference ability: The circuit design and signal processing algorithm of SERDES technology are also continuously optimized to improve its reliability and anti-interference ability. For example, the reliability and anti-interference ability of data transmission can be improved by adopting technologies such as forward error correction code (FEC) technology or adaptive equalizer.
SERDES technology is gaining importance in the field of high-speed serial interfaces, and it will continue to play an important role in driving the development of data centers, cloud computing and big data and other fields.
3. Development history
The development of SERDES technology can be traced back to the late 1980s, when SERDES technology was adopted in high-speed serial communication. The following is the main process of SERDES technology development:
Early 1990s: Application of SERDES technology in the storage field
First, use SERDES technology in the storage field, such as high-end disk arrays, SAN and other storage devices. These devices need to transmit large amounts of data at high speed and require high-speed serial interfaces to achieve long transmission distances.
Late 1990s: Application of SERDES technology in the field of network communication
With the development of Internet and local area network technology, network communication has become another important application field of SERDES technology. During this period, SERDES began to be widely used in various network standards, such as Gigabit Ethernet, Fiber Channel, and InfiniBand.
2000s: Adoption of SERDES Technology in Computing
As the performance of computer systems improved, SERDES technology began to be adopted in computing. For example, PCI Express and Serial ATA are high-speed serial interface standards based on SERDES technology to provide higher data transfer rates and better performance.
Contemporary: New Advances in SERDES Technology
SERDES technology continues to evolve as the technology evolves and the areas of application expand. For example, the reliability and anti-interference ability of data transmission can be improved by adopting technologies such as forward error correction code (FEC) technology or adaptive equalizer. At the same time, SERDES technology is continuously improving data transmission rate, reducing power consumption and cost, and expanding its application in various fields and scenarios.
SERDES technology continues to evolve and innovate, providing critical support and enablement for modern high-speed serial communications, networking and storage devices.
Currently, SerDes applications in the market mainly include Chip-to-Chip, Board-to-Board, Box-to-Box, etc., as shown in Figure 7 (a/b/c). And it has applications in large data centers, communication backbone networks, consumer electronics and other scenarios.
2. Serdes structure
Its structure mainly includes the following parts:
Clock Recovery Module (Clock Recovery Module)
The function of the clock recovery module is to extract the clock signal from the received serial data, so that the subsequent circuit can correctly analyze the received data. Clock recovery blocks are usually implemented using PLLs, DLLs, or other technologies.
Data Encoding and Decoding Module (Data Encoding and Decoding Module)
The data encoding and decoding module is usually used to encode the parallel data at the sending end into serial data, and decode the serial data received at the receiving end into parallel data. Common data encoding and decoding methods include 8b/10b, 64b/66b, etc.
Serializer (Serializer)
The serializer is generally located at the sending end, and its function is to convert parallel data into serial data and transmit it through the serial transmitter. The output rate of the serializer depends on parameters such as clock frequency and data encoding method, and usually can reach tens of Gbps.
Deserializer (Deserializer)
The deserializer is generally located at the receiving end, and its function is to convert the received serial data into parallel data for processing. The deserializer usually includes data decoding, clock recovery, data buffering and alignment, etc., which can realize high-speed and stable data transmission.
Clock Correction
In high-speed serial communication, due to the incomplete synchronization of the clocks at the sending end and the receiving end, the data may be displaced and jittered, resulting in an increase in the bit error rate. In order to solve this problem, Clock Correction technology can be used, which uses a specific algorithm to correct the clock at the receiving end so that it can be synchronized with the clock at the sending end, so that data can be received more accurately.
Channel bonding (Channel Bonding)
is a technology that binds multiple physical channels together to form a logical channel. In SerDes (Serializer/Deserializer), it can achieve higher bandwidth transmission by bundling multiple high-speed serial lanes together. Doing so can significantly increase communication speed and reduce the physical space occupied by channels. At the same time, it also helps to improve data reliability and fault tolerance, because even if one of the channels fails, the entire system can still continue to work.
The structure of SERDES mainly includes clock recovery module, data codec module, serializer and deserializer, etc. It is an indispensable key technology in modern high-speed serial communication and storage devices.
3. Application in the field of FPGA
In the field of FPGA, SERDES technology is mainly used in high-speed serial communication and storage interface, etc.: high-speed serial
communication
SERDES can convert parallel data inside FPGA into high-speed serial data, transmit it through PCB and other media, and then convert it into parallel data for processing. This method can greatly increase the data transmission rate, reduce power consumption and hardware cost, especially in scenarios such as high-speed network and optical fiber communication.
The memory interface
SERDES can also be used to connect FPGA and high-speed memory (such as DDR3/4) to realize high-speed and stable data transmission. In this scenario, SERDES can make full use of the bandwidth of the memory interface to improve memory read and write speed and system throughput.
Video signal processing
SERDES technology is also widely used in the field of video signal processing. For example, SERDES technologies such as D-PHY or TMDS (Transition minimized differential signaling) are used in the HDMI interface to realize the transmission and display of high-definition video data.
The high-speed bus interface
SERDES can also be used for the connection between FPGA and other high-speed bus interfaces (such as PCI Express, SATA, etc.). It can convert the data inside the FPGA into the serial data format required by these interfaces, realizing high-speed data transmission between the FPGA and external systems.
Many FPGAs of Xilinx have built-in one or more MGT (Multi-Gigabit Transceiver) transceivers, also called SerDes (Multi-Gigabit Serializer/Deserializer). The MGT transceiver includes high-speed serial-to-parallel conversion circuits, clock data recovery circuits, data encoding and decoding circuits, clock correction and channel bonding circuits, which provide the physical layer basis for various high-speed serial data transmission protocols. The TX transmitter and RX receiver of the MGT transceiver have independent functions, and both consist of two sublayers, the Physical Media Attachment (PMA) and the Physical Coding Sublayer (PCS), as shown in the figure below.
The PMA sublayer integrates a high-speed serial-to-parallel conversion circuit, a pre-emphasis circuit, a receiving equalization circuit, a clock generation circuit and a clock recovery circuit. The function of the serial-to-parallel conversion circuit is to convert the parallel data inside the FPGA into the serial data of the MGT interface. The pre-emphasis circuit is to compensate the high-frequency part in the physical connection system. A high-pass filter is added at the sending end to amplify the high-frequency components in the signal and improve the signal quality. However, the pre-emphasis circuit will increase power consumption and Electro Magnetic Compatibility (EMC), so it is generally shielded if it is not necessary. The receiving equalization circuit is mainly used to compensate the impedance difference caused by different frequencies. The clock generation circuit and the clock recovery circuit bind the clock and data at the sending end and then send it, and recover the clock from the received data stream at the receiving end, which can effectively avoid the clock jitter problem caused by the separate transmission of clock and data under the condition of high-speed serial transmission.
The PCS sublayer integrates 8B/10B encoding/decoding circuits, elastic buffer circuits, channel bonding circuits and clock correction circuits. The 8B/10B encoding/decoding circuit can effectively avoid continuous '0' or '1' in the data stream to ensure the balance of data transmission. The function of the channel bonding circuit is to bind multiple physically independent MGT channels into a sequentially logically synchronized parallel channel by adding K code characters in the transmitted data stream, thereby improving the throughput rate of transmission. The elastic buffer circuit is used to solve the problem of inconsistency between the recovered clock and the local clock, and can realize the channel bonding function by matching and aligning the K code in the buffer.
For specific timing analysis, you can refer to Xilinx's documentation on serdes (section 5, I have listed relevant documents)
The following figure is an interconnection demonstration of N pairs of SerDes transceiver channels, generally N is less than 4.
It can be seen that SerDes does not transmit clock signals, which is the most special feature of SerDes. SerDes integrates a CDR (Clock Data Recovery) circuit at the receiving end, and uses CDR to extract the clock from the edge information of the data and find the optimal sampling position.
SerDes transmits data in a differential manner. Generally, the data of multiple channels is placed in a group to share PLL resources, and each channel still works independently of each other.
SerDes requires a reference clock (Reference Clock), which is generally in the form of a differential to reduce noise. The reference clocks of the receiving end Rx and the transmitting end Tx can allow a frequency difference of hundreds of ppm (plesio-synchronous system), or they can be clocks of the same frequency, but there is no requirement for the phase difference.
For a simple comparison, a SerDes channel (channel) uses 4 pins (Tx+/-, Rx+/-), and the current FPGA can achieve up to 28Gbps. And a 16bits DDR3-1600 has a line rate of 1.6Gbps*16 = 25Gbps, but requires 50 pins. This comparison shows the advantages of SerDes in terms of transmission bandwidth.
Compared with the source synchronous interface, the main features of SerDes include:
SerDes is embedded in the clock in the data line, and does not need to transmit the clock signal.
SerDes can realize high-speed long-distance transmission through emphasis/equalization technology, such as backplane.
SerDes uses fewer chip pins
4. The relationship between Serdes and Lvds
After reading so much, you may be wondering, why are Serdes and Lvds so similar? What's the difference?
Both SERDES and LVDS are technologies used in high-speed digital signal transmission, and LVDS is one of the commonly used differential transmission methods in SERDES technology.
SERDES technology is a technology that converts parallel data into serial data and transmits it using differential signals. LVDS (Low Voltage Differential Signaling) refers to the technology of transmitting digital signals by comparing two different input voltages. Its core principle is to use a symmetrical multi-segment amplifier to ensure reliable transmission of differential signals, which can effectively resist the influence of electromagnetic interference, noise and other interference signals.
In practical applications, the differential transmission mode in SERDES technology can choose a variety of signal differential standards, among which LVDS is one of the widely used standards. For example, in some high-speed signal processing systems and communication fields, SERDES technology generally uses the LVDS standard to transmit differential signals, because LVDS has many advantages, such as small common-mode noise, strong anti-interference performance, and low power consumption. Therefore, SERDES technology is closely related to LVDS technology, and LVDS technology is also one of the commonly used differential transmission methods in SERDES technology.
Five, Xilinx documents about serdes
Xilinx official website provides a number of documents detailing the SERDES structure and application of 7 series FPGAs, the following are a few of them:
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
This user guide introduces in detail the SERDES structure using GTX/GTH Transceiver in Xilinx 7 series FPGAs, including communication interface, clock frequency, data codec, clock recovery, etc. Additionally, this document describes how to use the Vivado Design Suite for circuit design, implementation, and verification.
7 Series FPGAs Transceivers Wizard User Guide (this document, now incorporated in UG476, on page 27)
This user guide mainly introduces the configuration and optimization of 7 Series FPGAs SERDES using the Xilinx Transceivers Wizard tool. This document describes in detail how to use the Transceiver Wizard tool, supported protocols, performance parameters, etc., and provides sample designs and experimental procedures.
7 Series FPGAs SelectIO Resources User Guide (UG471)
This user guide mainly introduces the SERDES structure using SelectIO technology in 7 Series FPGAs. This document details the implementation methods and techniques of SelectIO data encoding and decoding, clock recovery, etc., and also provides multiple use cases and design suggestions.
7 Series FPGAs PCB Design Guide (UG483)
This PCB design guide mainly introduces the PCB layout and routing specifications that need to be paid attention to when designing SERDES in 7 Series FPGAs. This document details implementation methods and techniques for PCB signal integrity, EMI suppression, clock distribution, etc., and also provides several design recommendations and best practices.
6. References
1. SerDes overview
2. SERDES key technology summary
3. FPGA SerDes interface