Do less questions today, organize the projects
FPGA project: Use FPGA to implement edge detection for face recognition.
IC Verification Items: 9
Verilog
1、
Principle: Exclusive or each bit must be XORed, and the multi-bit side is 1'b0/1'b1, and the output result of 0 or 1 can be completed. At this time, it has nothing to do with always@, which can be defined by the wire variable, judged according to the value of sel, and determined according to the diagram.
If there is more than one statement after if and else, be sure to add begin end
"~" will invert each bit of the variable in turn, such as: a[3:0] ={1,0,0,1}, ~a ={0,1,1,0}; "!" will treat the variable as a value, and if it is not 0, it
is 1
Method 2 is to use always. When using always, there must be a reg variable. Wire is used for combination variables and cannot be mixed.
if (sel) here sel is either 0 or 1, no assignment is required.
2、
python
1、