HDLbits--Cs450/counter 2bc

Directly output according to the logical expression without using the state machine writing method 

Build a two-bit saturating counter.

When train_valid = 1 and train_taken = 1, the counter is incremented (up to 3). It is decremented (down to a minimum value of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value.

AreSet is an asynchronous reset that resets the counter to Weak Not Taken (2'B01). The output state [1:0] is a two bit counter value.

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    always@(posedge clk,posedge areset)
        begin
            if(areset)
                state<=2'b01;
            else
                begin
                    if( train_valid)
                        begin
                            if(train_taken)
                                begin
                                    if(state<3)
                                        state<=state+1'b1;
                                    else
                                        state<=2'b11;
                                end
                            else
                                begin
                                    if(state>0)
                                        state<=state-1'b1;
                                    else
                                        state<=0;
                                end
                        end
                    
                    else
                        state<=state;
                end
            
        end
            
                                    

endmodule