Table of contents
1. Detailed explanation of the principle and usage steps of the ECG monitor
(1) Basic composition of the system:
(2) Structure and principle of portable remote ECG monitor
(3) Structure and principle of portable ECG monitor
2. Portable ECG monitor design
2.1 Input buffer circuit and preamplifier circuit design
2.3 Post amplifier circuit design
2.5 Schmitt trigger circuit design
3 Design of system software part
3.1 Brief introduction of LCD, keyboard, timer and AD module
3. ECG monitor solution based on DSP system platform
4. Development of a new embedded ECG monitor based on ARM7
2. The working principle of the system
3. System hardware module design
3.1, signal conditioning circuit
3.2. Embedded processor and peripheral circuits
3.2.2, system program memory Flash ROM and SDRM expansion
3.2.3, liquid crystal display LCD and keyboard module
4.1. Transplantation of embedded uClinux operating system on S3C44B0X
4.2. Realization of embedded GUI based on S3C44B0X
4.3. Implementation of RTL8019AS driver under uClinux
5. Design scheme of main control system of medical ventilator based on SOPC technology
6. Ultrasonic motor drive control circuit based on NiosⅡ
1 Design of the drive controller
1.2.1 Construction of Nios Ⅱ system
1.3 Control mode of drive controller
2.1 Research on speed stability of ultrasonic motor
1. Detailed explanation of the principle and usage steps of the ECG monitor
With the development of medical technology, ECG monitors are widely used in the monitoring of clinical conditions. By viewing the physiological parameters monitored by it , in addition to providing reasonable and objective evidence for medical staff, it is very important for early detection of changes in the condition and prevention of complications. It has played an important guiding role, allowing medical staff to take effective treatment measures and treatment methods for patients with changing conditions faster and better, and achieve the goal of ensuring the safety of patients. It is precisely because this kind of equipment facilitates the monitoring of the patient's condition by the medical staff, and the treatment of the patient can be more rapid and effective. Therefore, it is widely used in various hospitals. Engineers engaged in the medical electronics industry may have a good understanding of this aspect of knowledge, and some may have a half-knowledge, including what is an ECG monitor , its basic principles, working principles, correct use steps, and precautions for use, etc. Let's learn this kind of equipment in depth from its basic principles and usage steps.
What is an ECG monitor
What is an ECG monitor? It is an important application of a monitor (what is a monitor). As a commonly used device in hospitals, it can simultaneously monitor the patient's ECG, respiration, blood pressure, body temperature, pulse and other physiological parameters . Practical medical instrumentation for precision testing and measurement. It intuitively displays the data that needs to be detected and monitored on the monitor for the hospital staff to judge and treat patients. Each physiological parameter that can be monitored is generally set with a safety value for reference and comparison. If the actual value of the patient is not within the safety value, an alarm will be automatically issued.
Principle of ECG monitor
(1) Basic composition of the system:
(A) cathode ray oscilloscope
(B) ECG recorder
(C) Pressure monitor
(D) Breathing monitor
(E) Body temperature monitor
(F) Composition of computer processing system
The electrocardiographic activity is transmitted to the processor through the ECG lead wire, and the blood pressure is converted into an electrical signal by the pressure sensor and transmitted to the processor. Respiratory activity is caused by exhalation and inhalation, and the change of thoracic resistance is transmitted to the processor through the ECG lead and the ECG activity at the same time. The processor amplifies the electrical signal from the patient's body, and after processing by the microcomputer, it becomes a waveform output and a digital signal. The output is displayed on the screen of the cathode ray oscilloscope through the photoelectric display system, and its working principle is an important reference for the design of the ECG monitor.
(2) Structure and principle of portable remote ECG monitor
It is mainly composed of four key modules: the front-end acquisition and conditioning module of ECG signal, the ECG signal processing and storage module, the data display module and the remote transmission control module. The functional structure of the system is shown in the figure. Its hardware platform adopts CycloneII 2C35 FPGA chip, adopts SOPC technology to integrate NiosII soft-core processor, memory, functional interface and expansion I/O port, etc. on one FPGA chip, and peripherally expands ECG data acquisition board, network, LCD screen, The hardware architecture of the system is realized by touch screen/keyboard, SD memory card and other hardware, and it has an expandable I/O interface, which is convenient for future system function upgrade and expansion.
Structure and Principle Diagram of Portable Remote ECG Monitor
(3) Structure and principle of portable ECG monitor
The system hardware module mainly includes: signal conditioning circuit (amplifier, band-pass filter, notch filter), embedded processor and peripheral circuit (A/D conversion, Flash ROM and SDRM expansion , liquid crystal display LCD and keyboard module, Ethernet module) in two parts . Its structure and principle diagram are as follows:
Structure and Principle Diagram of Portable Remote ECG Monitor
After the ECG signal is collected from the left and right arms of the person through special electrodes, it is sent to the signal conditioning circuit , firstly amplified by the preamplifier , filtered by the high-pass filter to filter the DC signal and low-frequency baseline interference, amplified by the post-stage amplifier , and then passed through the The filter further filters out the 50HZ power frequency interference , and the ECG signal that meets the requirements is obtained after the low-pass filter , and is sent to the ADC from the analog signal input terminal for high-precision A/D conversion. We also introduced a right leg drive circuit and a lead-off detection circuit in the circuit.
ECG monitor use steps
(1) ECG monitoring
At present, the color of the electrocardiogram lead wire telegram has been standardized to reduce confusion, and the positive, negative and ground electrodes are placed according to the diagram.
(2) Pressure monitoring must perform the following operations in order to obtain correct data and waveforms
(A) Transducer placement at the level of the right atrium
(B) Zero setting step, various types of monitors are equipped with a zero button.
(C) The entire pressure measurement pipeline is filled with heparin saline to prevent blood clots from clogging, and the pipeline system must not contain air bubbles.
(D) Regularly flush with heparin saline or continuously flush with a micropump at a rate of 2ml/h to maintain the patency of the pipeline.
(2) The operating procedure is as follows:
(A) Connect the ECG monitor power supply.
(B) Place the patient in supine or semi-recumbent position.
(C) Turn on the main switch.
(D) Wipe the skin of the patient's chest where the electrode is attached with a saline cotton ball.
(E) Paste the electrodes, connect the ECG lead wire, and the ECG oscillogram will appear on the screen
(F) Tie the cuff up to two fingers above the elbow fossa. Press Measure—Set Alarm Limit—Measure Time.
epilogue
With the development of modern medical technology and current medical monitoring technology, ECG monitors have become an indispensable category of medical electronic equipment, and play more and more important roles in hospitals. It has the advantages of simple operation , It is easy to view and record, can monitor many physiological parameters, and has a wide range of applications and places , and has attracted much attention in medical treatment applications.
2. Portable ECG monitor design
Abstract: Based on the research on ECG signal acquisition and processing technology, a low-power, real-time portable ECG monitoring system is designed in combination with MSP430F149 single-chip microcomputer . First, the hardware circuit is used to collect, amplify, filter, and denoise the ECG signal , and then use MATLAB to realize the simulation of digital filtering and denoising of the ECG signal. Finally, the single-chip program is written and debugged, mainly to complete the heart rate test, ECG recording and simple Analysis and other functions.
Citation address of this article: Design of Portable ECG Monitor
1 Overall system design
The ECG signal is a very weak physiological signal, which is easily disturbed by the surrounding environment. In order to make the ECG more accurate and clear, the system uses a combination of analog filtering and digital filtering to process the ECG signal. The ECG signal is collected through the heart electrode, and the collected ECG signal enters the preamplifier through the input buffer circuit. After the preamplifier is amplified, the signal enters the processing circuit. In the processing circuit, it goes through high-pass, low-pass, 50Hz notch, post-stage amplification, level up, Schmitt trigger, and finally enters the microcontroller for processing . Before the single-chip processing, with the help of the MATLAB simulation platform, first perform FIR filtering and notch processing on the ECG signal in the arrhythmia research database (MIT-BIH) provided by the Massachusetts Institute of Technology, and obtain the C of the best digital filter. code. Then the microcontroller is controlled by programming to complete the following functions: timing, interruption, heart rate measurement, AD conversion, sampling, digital filtering, noise removal, electrocardiogram display , and simple analysis. The overall design block diagram of the system is shown in Figure 1.
2 System hardware design
Large-scale medical electrocardiographic equipment can use a variety of lead methods to obtain electrocardiographic signals, and various signals obtained can be displayed in real time on the monitor. Considering the convenience of portable devices, the system uses standard leads to collect one ECG signal, that is, three electrodes are used to obtain ECG signals. Considering the characteristics of the ECG signal, the hardware circuit part should meet the following requirements:
(1) Gain. The amplitude range of a normal ECG signal is 10μV-4mV, and the typical value is 1mV. The conventional design of the ECG amplifier gain requires that when the input is 1mV, the output level should reach about 1V, so the amplification factor of the ECG amplifier should be about 1000 times.
(2) Frequency response. The spectrum range of the ECG signal is 0.05-100 Hz, and the spectrum energy is mainly concentrated between 0.05-40 Hz, so the frequency band range must be at least 0.05-40 Hz. Therefore, a bandpass filter should be designed to compress the passband.
(3) High input impedance. The ECG signal obtained through the ECG electrodes is very weak, and the human body has a large source impedance, so the source impedance of the amplifier must be increased to ensure the stability of the gain.
(4) High common mode rejection ratio. The contact between the electrodes and the skin and the interference of the mains will cause common-mode interference. If a circuit with a high common-mode rejection ratio is not designed, the weak ECG signal will be overwhelmed.
(5) Low noise and low drift. Due to the high gain, noise and drift will also affect the acquisition of ECG signals. Therefore, in order to obtain high-quality ECG signals, low-noise components should be used and low-temperature drift circuits should be designed.
(6) High security. The use of any instrument must take the safety of the human body as an important indicator, and avoid electric shock to the human body.
2.1 Input buffer circuit and preamplifier circuit design
In the whole circuit design, the input circuit adopts buffer stage circuit. In terms of signal amplification, a two-stage amplification method is used. The input buffer circuit can increase the input impedance of the entire amplifier circuit and reduce the output impedance. In this way, a higher-amplitude signal can be obtained in the subsequent matching resistor network. The preamplifier circuit adopts AD620 as the core device.
AD620 has the following characteristics:
(1) AD620 has low cost, high precision, high input impedance, and high common-mode rejection ratio. It only needs to change the resistance Rg (R6 in Figure 2) to realize the change of the amplification gain between 1-1000;
(2) AD620 is small in size and low in power consumption, so it is very suitable for battery-powered portable equipment;
Citation address of this article: Design of Portable ECG Monitor
(3) AD620 has high precision, small input bias current, low offset voltage, and low offset drift, making it an ideal choice for data acquisition systems.
In a word, the characteristics of AD620 low noise, low input bias current and low power consumption meet the requirements of this system, and the signal distortion after AD620 amplification is very small, which is very suitable for ECG (electrocardiogram) application . Design simulation circuit shown in Figure 2. In the figure, pin 3 is the positive input terminal of the amplifier, connected to the input signal of the left arm; pin 2 is the negative input terminal of the amplifier, connected to the input signal of the right arm; pin 7 is connected to +3V/+5V The working voltage of the 4 pins is -3V/-5V; the idle 4 pins are grounded, this is done to improve the anti-interference performance of sensitive devices, and then improve the anti-interference ability of the entire system; between l and 8 pins Between external resistor Rg (Figure 2 R6), by changing the size of the resistor can adjust the amplification gain. The relationship between resistance Rg and gain G is as formula (1):
According to experience, the gain of the preamplifier is generally 8-l0 times to prevent the saturation of the preamplifier circuit. In this system, a 5.1kΩ resistor is connected between pins 1 and 8, so that the preamplifier has a 10-fold magnification.
2.2 Filter circuit design
According to the requirements of frequency response, the filter design is shown in Figure 3.
The parameters of the high-pass filter circuit are:
Eigenfrequency:
2.3 Post amplifier circuit design
Since the total voltage magnification of the ECG signal amplifier is required to be 1000 times, and the pre-stage magnification is 10, the voltage magnification of the post-stage amplifier is 100 to meet the requirements.
Citation address of this article: Design of Portable ECG Monitor
As shown in Figure 4, the magnification:
2.4 Level up circuit design
The ECG signal amplified and filtered by the analog circuit is an AC signal, and the conversion range of the MSP430 series single-chip microcomputer is a positive voltage signal (0~3.3V), so it is necessary to raise the analog signal to above 0V and turn the bipolar signal into a single polarity signal. The circuit design is shown in Figure 5.
2.5 Schmitt trigger circuit design
After the ECG signal is amplified by 1000 times, the peak value can reach 4V at most, and the Schmitt trigger can be used for waveform transformation to convert the ECG signal into a rectangular wave. The rectangular wave will have a falling edge and a rising edge, as long as the falling edge or rising edge interrupt in the microcontroller is called , the number of heartbeats can be recorded. The Schmitt trigger is built on the basis of the 555 timer. The circuit design is shown in Figure 6.
3 Design of system software part
The flow chart of the system software is shown in Figure 7. Firstly, the function menu is displayed on the liquid crystal of the single-chip microcomputer , and two function options are provided for the user: heart rate measurement and electrocardiogram recording. After entering the heart rate measurement interface, start the timer and start the recording. The heart rate value will be displayed after recording 4 heartbeats. After each display, the record will be refreshed to display the result again, mainly to make the result more accurate. During the recording period, you can press the button to end the measurement, and return to the main menu directly after the heart rate test is completed. After entering the ECG recording page, start AD initialization, the system automatically completes AD conversion, value extraction, FIR filtering, and finally displays the ECG . After displaying the ECG, the user can return to the main menu by pressing the key.
3.1 Brief introduction of LCD, keyboard, timer and AD module
Citation address of this article: Design of Portable ECG Monitor
MSP430F149 provides two LCD interfaces: 1602 LCD interface and 12864 LCD interface. Because the interface of 1602 liquid crystal is small, it is not easy to display ECG , so 12864 liquid crystal is used. The initialization of the liquid crystal can be completed by writing instructions to the controller.
The MSP430F149 development board comes with 4 buttons, which are connected to P1.0-P1.3 by default. The principle of the 1X4 keyboard scanning program is relatively simple. First, give these four buttons a high level, and then detect the level of the P1.0-P1.3 port. Once a key is pressed, the corresponding port level will change. Through the program detection Level, so that you can know which key is pressed.
There are three timers in MSP430F149: watchdog timer, timer A, and timer B. Here, timer A is used. Timer A has the following characteristics: 16-bit counting/timer, 4 modes in total; you can choose to set the clock source; multiple capture/compare registers; asynchronous input/output latches; interrupt vector registers, which can be quickly decoded Interrupt generated by Timer A.
The integrated ADC12 module within MSP430F149 can perform A/D conversion. The ADC12 module is a 12-bit precision A/D conversion module, which has the characteristics of high speed and versatility.
3.2 FIR filter design
Filter the ECG signal with the help of MATLAB platform . Import the original ECG signal in MATLAB , design different orders of FIR filters, process the original ECG signal , and compare the results. The processing result of the filter is shown in Fig. 8, it is obvious to choose the 3rd order FIR filter.
3.3 ECG display results
After debugging the hardware circuit and writing the software program, the ECG signal shown in Figure 9 is obtained on the LCD.
4 Conclusion
The system designs a portable electrocardiograph based on the single- chip microcomputer. A large number of experiments and applications have shown that the hardware circuit part can accurately complete signal acquisition, amplification, filtering and other processing; the software part can accurately measure and display heart rate with the help of MSP430 operating platform and MATLAB signal processing program, but it is not in the function of displaying ECG . Perfect, needs further improvement. Because the system is small in size, low in cost, easy to use and accurate in measurement data, it can provide heart monitoring function for people.
3. ECG monitor solution based on DSP system platform
Solution of ECG monitor based on DSP system platform
4. Development of a new embedded ECG monitor based on ARM7
Abstract : This paper introduces the software and hardware design of a new type of portable ECG monitor. The 32-bit low-power microprocessor based on ARM core is used as the system control core. The system adopts the embedded uClinux operating system with open source code to realize ECG The real-time display and remote monitoring of signals has the advantages of lightness, energy saving, powerful functions, safety and stability.
Keywords : ECG, ARM uClinux, liquid crystal display, TCP/IP protocol
1. Introduction
Cardiovascular disease is currently the most harmful disease to human beings, and electrocardiogram is the main means and basis for checking, diagnosing and preventing such diseases. Because the traditional ECG monitor based on PC platform is expensive, bulky, inconvenient to move and mainly concentrated in large hospitals, it cannot monitor the patient's condition in real time, which brings great inconvenience to doctors and patients. In recent years, with the rapid development of embedded and network communication technology, we have developed a new type of embedded ECG monitor based on ARM7 processor, which uses a 32-bit high-speed processor of Samsung's ARM7TDMI core RISC S3C44B0X, with the advantages of low cost, small size, high reliability, and simple operation, is suitable for individuals, small and medium-sized hospitals and community medical units, and provides good help for emerging medical approaches such as home health care (HHC) and telemedicine (Telemedicine) with support.
2. The working principle of the system
Figure 1 The system structure block diagram of the new embedded ECG monitor
After the ECG signal is collected from the left and right arms of the person through special electrodes, it is sent to the signal conditioning circuit, firstly amplified by the preamplifier, filtered by the high-pass filter to filter the DC signal and low-frequency baseline interference, amplified by the post-stage amplifier, and then passed through the The filter further filters out the 50HZ power frequency interference, and the ECG signal that meets the requirements is obtained after the low-pass filter, and is sent to the ADC from the analog signal input terminal for high-precision A/D conversion. In order to better suppress the interference signal and prevent the lead from loosening and falling off, we also introduced the right leg drive circuit and the lead off detection circuit in the circuit. The system control core adopts Samsung's S3C44BOX, and the liquid crystal display (LCD) establishes a good human-computer interaction interface. The collected signals can be displayed and played back in real time through the LCD, and the data is transmitted through the Internet based on TCP/IP (Transmission Control Protocol, Internet Protocol) Sequentially and reliably transmit data to the ECG monitoring center, providing a reference for medical staff to make timely and accurate diagnoses. The embedded real-time operating system adopts the popular uClinx, manages and coordinates the work of each module, and provides guarantee for the reliable operation of the system.
3. System hardware module design
3.1, signal conditioning circuit
The signal conditioning circuit mainly includes: amplifier, bandpass filter, notch filter, etc.
Figure 2 ECG preamplifier circuit
The human ECG signal is a low-frequency weak signal in the background of strong noise, generally only 0.05-5mV, the spectrum range is: 0.05-100HZ, the amplitude of the ECG signal is about 1mV when it is output normally, and the input voltage of the A/D converter The level is required to reach about 1V, that is, the ECG amplification factor is about 1000 times. Since myoelectric interference may cause the shift of the static operating point of the preamplifier, or even reach saturation, the gain of the preamplifier should not be too large. We choose AD620 instrumentation amplifier as the system preamplifier, it has the characteristics of low noise, low drift, high common mode rejection ratio, high input impedance and so on. Its gain is adjusted by the resistance Rg of pin 1 and pin 8, which can reach 1-100 times. The calculation formula is: G＝49.4/Rg+1. I design the primary magnification to be around seven levels, select a precision wirewound resistor with a precision of 0.01% and a resistance of 8.25, and use TL064 in the latter stage to amplify the signal to the input level requirements of the A/D converter.
Figure 3 ECG post-amplification and filter circuit
In order to suppress DC drift and low-frequency noise outside the passband of the amplifier, an RC high-pass filter is designed; because the frequency of the ECG signal is below 100HZ, a low-pass filter and a bandband filter are also designed to eliminate high-frequency signals and 50HZ power frequency interference. blocking filter.
In order to prevent the lead from loosening and falling off, a lead detection circuit is designed. When the electrode falls off, the output level of the comparator changes from a normal high level to a low level, and an alarm signal is generated to remind the patient to check the lead. In the right leg drive circuit, after the common mode voltage of the human body is detected, it is amplified and fed back to the right leg of the person through inversion, but not directly connected to the ground of the amplifier, so that the displacement current of the human body does not flow to the ground, but to the transport amplifier output, the AD620 reduces the common-mode voltage pickup.
3.2. Embedded processor and peripheral circuits
S3C44B0X is a microprocessor solution that Samsung provides cost-effective and high-performance for handheld devices and general types of applications. The CPU core adopts the 16/32-bit ARMTDMI RISC processor (66HZ) designed by ARM Company, the operating voltage of the core is 2.5V, with 8KB high-speed cache, 8 banks of external storage controllers, a total of 256MB, 8-channel 10-bit ADC and Support color/black and white display LCD controller, with normal, slow, idle and stop power consumption control modes, streamlined and excellent full static design suitable for low-cost and power-sensitive designs.
3.2.1, A/D conversion
The consideration of the accuracy of the ECG signal is mainly due to the requirements for the analysis and processing of the abnormality of the ST segment. It has been recognized that the level change of the ST segment is 0.05mV, so the sampling accuracy is at least 0.025mV. According to the American Heart Association AHA standard and Nyquist sampling law, when the signal sampling frequency is equal to or greater than twice the highest frequency of the signal, the original signal can be restored from the sampled signal without distortion. The ECG frequency range is 0.05-100HZ, and we take the sampling frequency as 200HZ, that is, the sampling period is 5ms. S3C44B0X has a 10-bit ADC with successive approximation 8-channel analog signal input, and the input full-scale voltage is 2.5V, which can be distinguished The minimum value of the input voltage change is 2.5V/210=2.5mV, the magnification of ECG acquisition is about 1000 times, and the minimum resolution of the input terminal is about 2.5mV/1000=0.0025mV, so it fully meets the requirements of the system.
3.2.2, system program memory Flash ROM and SDRM expansion
S3C44B0X itself does not have ROM, so an external ROM device must be connected to store program codes and data that still need to be saved after power failure. We have adopted the CMOS multi-purpose Flash ROM with the capacity of 1MB×16 that SST Company puts out, it has advantages such as good reliability, low power consumption, and fast reading speed. After the system is reset, it starts to execute from address 0X00000000. The system startup code should be stored at this address, so the Flash is mapped in the Bank0 area of the processor.
A SDRM L43L16064 with a capacity of 8MB from Linksmart is used as the running space, data area and stack area of the system program for fast reading and writing of the system. Its storage method is 4Bank×1MB×16, adopts multi-Bank and pipeline structure, and has automatic refresh, low power consumption and power-down mode. Its storage space is mapped on Bank6 of S3C44B0X, and the address range is: 0XC000000H-0XCFFFFFFH.
3.2.3, liquid crystal display LCD and keyboard module
In order to enable users to have an intuitive impression and common sense observation of the collected ECG signals, we have adopted EPSON's EG1147 FSTN monochrome LCD display module to monitor the time, waveform, ECG parameters and system menus. display, and at the same time cooperate with the keys to control and set the instrument. Its display dot matrix is 240×320, adopts EL backlight, and has its own driver. By programming the built-in LCD controller of S3C44B0X, the image data located in the display buffer of the memory is transmitted to the driver of the external LCD. PC port Use the PD port as the LCD driver interface, set the PC port to work in the third functional state, and the PD port to work in the second functional state.
3.2.4, Ethernet module design
S3C44B0X does not have an integrated network interface controller NIC (Network Interface Controller), so we have extended a Realteck company's RTL8019AS controller for the system, which is compatible with NE2000, has good software transplantation, and simple interface circuit. RTL8019AS working principle: the driver program writes the data to be sent into the chip according to the specified format and starts the sending command. On the contrary, when the chip receives signals from the physical channel, it will directly convert them into data in the corresponding format according to the Ethernet protocol, and send an interrupt to request the CPU to read the data.
4. System software design
The software design mainly includes the transplantation of embedded operating system uClinux on S3C44B0X, the collection and storage of ECG data, the realization of embedded GUI based on S3C44B0X, and the development of network device drivers.
4.1. Transplantation of embedded uClinux operating system on S3C44B0X
uClinux is a free and open-source operating system designed specifically for processors without MMU (Memory Management Unit). It supports multi-tasking and adopts modular design. System transplantation can be divided into two parts: bootloader and kernel transplantation.
Essentially speaking, the Bootloader does not belong to the system kernel, and starts running after the CPU is powered on, creating an initialization environment and booting the kernel. This part of the code is written in assembly language, mainly to complete the hardware initialization, initialize and set the memory map of the system, and change the PC value at the same time, so that the CPU starts to execute the kernel of the operating system from SDRM.
When transplanting the kernel, first download the source code file package in the RedHat Linux environment to establish a cross-compilation environment, and then enter the uClinux-dist folder to configure the kernel. The system configuration is mainly composed of three parts: Makefile, configuration file (config.in) and configuration tool ( in the /script directory). Run the make menuconfig command, the top-level menu will appear, select the hardware system, kernel version and C library, here we choose Samsung's S3C44B0X for vendors, Linux-2.4-x for the kernel version, and uClibc for the C library. Then modify the source code, corresponding to the subdirectories of each hardware, for example, modify or add drivers in uClinux-dist/linux-2.4-x/drivers/; save the settings and exit, then execute the make dep and make lib_only commands to generate C library; run make user_only to generate the application program; then run make romfs and make image to generate the rom file system, copy the kernel file to uClinux-dist/images; finally run make to generate the kernel file that can be run by the embedded system, this Three files can appear in uClinux-dist/images: "rom" is the compressed kernel, "ram" is the directly running kernel, and romfs.img is the file system of uClinux. The "ram" and "rom" files can be downloaded from the serial port of the PC to the memory of the embedded system and run directly through the hyperterminal. At this time, the uClinux startup information will also be displayed on the hyperterminal.
4.2. Realization of embedded GUI based on S3C44B0X
The program design of the screen driver is mainly the structure pointer of PSD (Pointer to Screen Device). The structure pointed to by the pointer records all relevant attributes, and judges which sub-function is selected according to the display attribute to provide the relevant display function. The graphics engine calls PSD to complete drawing functions such as rectangle and circle, and these functions call the basic drawing functions of the underlying screen driver to complete the graphics display.
4.3. Implementation of RTL8019AS driver under uClinux
In uClinux, a network interface is regarded as an entity that sends and receives data packets, represented by a net_device data structure, and various operations on the network interface are defined in the data structure. The program is modified on the basis of the uClinux network driver file, mainly modifying two files under /drivers/net: ne.c and 8390.c, including most of the work such as chip initialization, packet receiving, network registration, etc. . The kernel will automatically call the function ne_probe() during initialization, read the RTL8019AS identification register, detect whether the device exists to determine whether to start the driver, configure and initialize the hardware, and then initialize the variables in the net_device structure, and then call Rtl8019as_init() to do RTL8019AS Register related settings, and finally start and close RTL8019AS according to the value of starp.
5. Conclusion
In view of the extremely weak ECG signal and the characteristics of being easily disturbed by the outside world, the innovation of this paper is to use the instrumentation amplifier AD620 with low drift and common mode rejection ratio for primary amplification of the signal, and design the right leg drive circuit to enhance the signal. Anti-interference ability; the introduction of LCD gives people an intuitive impression and common sense judgment; the collected data can be transmitted to the remote data center in real time through Ethernet for expert analysis and diagnosis; the introduction of embedded uClinux ensures the stability and reliability of the system The operation; the miniaturized design is more conducive to the patient's carrying. As the incidence of cardiovascular diseases continues to increase year by year, this portable ECG monitor has high application value and good market prospects.
5. Design scheme of main control system of medical ventilator based on SOPC technology
A ventilator is an instrument that can replace or assist a person's breathing function. It is suitable for artificial respiration for patients with respiratory failure or even stop breathing. It can help patients correct hypoxia and discharge carbon dioxide, and is an important tool to save the lives of some critically ill patients.
Citation address of this article: Design scheme of main control system of medical ventilator based on SOPC technology
Most of the main control systems of existing ventilator products are implemented based on single-chip microcomputers. For products with stronger functions, high-end single-chip microcomputers are required, which makes the cost of the system relatively high, and there are many peripheral interface modules and complex structures. Using SOPC (System on Programmable Chip) technology to design the main control system can make full use of the powerful functions of the IP core, reduce the number of peripherals, and at the same time only occupy a small part of resources, which greatly improves the cost performance of the system.
This paper uses SOPC technology to design the main control system of the continuous positive airway pressure ventilator , using Altera's Nios II soft-core processor and some general IP cores, the author customizes the components based on the Avalon bus specification, and integrates all control logic Integrated into a single FPGA.
Positive pressure ventilators send air into the lungs by increasing the pressure in the airways, and the increased pressure in the lungs expands the lung cavities. When the pressure is lost, due to the elasticity of the lung tissue, the lungs are restored to their original shape, and part of the exchanged air is exhaled from the body. At present, most ventilators use this method of increasing the pressure in the airway to deliver air to the patient.
The air pressure required by the ventilator is provided by a DC motor, and the control signal of the DC motor is a PWM signal, and the speed of the motor is controlled according to the duty cycle and period of the PWM signal. The external interface provides buttons to accept commands and set various parameters. Prompt information, status information, and parameter information are displayed through character LCD. For the convenience of testing the system, UART is used as the command control interface to directly control the system, and the interface is hidden after the finished product.
system structure
The block diagram of the ventilator main control system with SOPC technology as the core is shown in Figure 1.
Fig.1 Hardware structure block diagram of ventilator system
The core FPGA of the main control system adopts EP1C6T144C8 of Cyclone series of Altera Company . The CPU is the Nios II soft-core processor, which manages the entire system in a unified manner. The main control board is inside the folded line box. Except for the PC for downloading and debugging, the DC motor and the main control board need to be powered separately. After the DC motor works, the airflow is sent to the mask, and the motor adjusts the size of the airflow according to the signal from the terminal. A pressure detection module is installed in the mask, which is returned to the main control board through A/D conversion, and used to feedback and adjust the airflow. The mask is for patient use.
DC motor control
The system uses PWM signal to control the DC motor. There is no PWM component in the standard IP core provided by SOPC Builder, and it needs to be customized. The output signal of the PWM component is a square wave, and the period and duty cycle of the square wave are adjustable. The logic structure of PWM task is shown in Fig. 2.
Figure 2 PWM task logic structure
The task logic of the PWM component is:
●PWM task logic consists of an input clock, an output signal, an enable bit, a 32-bit counter and a 32-bit comparator;
●The clock drives the 32-bit counter to establish the period of the output signal;
The comparator is used to compare the current value of the 32-bit comparator with the duty cycle value to determine the output signal;
●If the current value is less than or equal to the duty cycle value, the output logic signal is 0, otherwise it is 1.
Register file for PWM component:
●clock_divde is the number of clock cycles in one cycle of PWM;
●duty_cycle PWM output is the number of clock cycles of low level;
●enable PWM output permission/prohibition. A rising edge from 0 to 1 enables the PWM component.
The header file and driver package of the PWM definition register are:
altera_avalon_pwm_init(); //PWM module initialization, including period setting
altera_avalon_pwm_enable(); //PWM module enable
altera_avalon_p wm_disable(); //PWM module disabled
altera_avalon_ pwm_change_duty _cycle(); //PWM module duty cycle adjustment
For DC motors, the PWM duty cycle needs to reach a certain amount to make the motor work. The PWM signal below the threshold (PWM_DUTY_THRESHOLD) cannot drive the motor, and this part of energy will be converted into heat and damage the motor. Therefore, when setting the PWM value It should be noted that the value is set above the threshold, and the set value is judged in altera_avalon_pwm_change_duty_cycle(). If the value is lower than PWM_DUTY_THRESHOLD, it is adjusted to PWM_DUTY_THRESHOLD+1.
After all the above designs are completed, they are packaged into SOPC components in SOPC Builder.
Output and Indication Module
The system needs to input settings, control and display prompts. This part of the function includes key input, LED indicator output, buzzer output, LCD output, etc.
6. Ultrasonic motor drive control circuit based on NiosⅡ
The ultrasonic motor is a new type of micro motor. Its working principle is to make the stator vibrate slightly in the ultrasonic frequency range through the inverse piezoelectric effect of the piezoelectric material, and convert the vibration into the rotary (linear) motion of the mover by friction. Ultrasonic motors have the advantages of small size, light weight, compact structure, fast response, and no electromagnetic interference. They have broad application prospects in aerospace and military equipment and other fields.
In recent years, China has put forward some control theories in the aspect of ultrasonic motor control, and built some actual driving and control circuits for ultrasonic motor drive. In 2010, Master Xue Wenyu studied the ultrasonic motor drive controller based on DSP chips, but the drive circuit is still dominated by traditional analog circuits, the precision is not high, and the frequency and phase can not be adjusted in real time. In 2011, Master Sun Lin studied the ultrasonic motor drive controller based on DSP/FPGA, and used DDS technology to generate digital sine waves. Although the accuracy and real-time performance were improved, a lot of logic resources of the chip were wasted, and it was not conducive to drive control. Circuit miniaturization.
This article uses Altera's EP3C400240C8 chip to design a new ultrasonic motor drive controller with FPGA as the core, SOPC technology and Nios II soft-core processor . In the FPGA, a Nios II soft-core processor is customized with the idea of SOPC (system on a programmable chip) as the control operation part, and the DDS module and the grating feedback counting module with adjustable frequency, phase and amplitude are written in Verilog language. A closed-loop system has good flexibility and reconfigurability while satisfying the control accuracy and real-time performance, and it can control the operation of the ultrasonic motor with very few hardware resources and a highly integrated system structure, which is convenient for the drive control circuit. miniaturization.
1 Design of the drive controller
1.1 Drive control circuit
The ultrasonic motor drive control system proposed in this paper is composed of a control driver and a power amplifier/boost circuit. Figure 1 is an ultrasonic motor drive control circuit built with FPGA as the core. The driving mechanism of the ultrasonic motor requires that the driver must provide the same frequency and equal amplitude sinusoidal alternating current with a certain phase difference between the two phases in the ultrasonic frequency band, and the voltage is between tens of volts and hundreds of volts. The functions of this circuit are all realized by FPGA software, controlling and outputting sinusoidal alternating current, which greatly improves the stability and accuracy of the control system, and greatly reduces the area of the control system circuit board. One control board can control several ultrasonic waves at the same time. motor.
This drive control system uses the DDS module programmed inside the FPGA to output two channels of sine wave data with a certain phase difference, and then converts it into a sine wave signal through the DA chip. After power amplification, the voltage is raised by a transformer.
The output waveform of the circuit after loading the ultrasonic motor is shown in Figure 2, and the waveform becomes much smoother. When the frequency of the ultrasonic motor drifts during operation, the system can also adjust the corresponding drive output from the change in speed, and there will be no phenomenon of unstable motor speed.
1.2 FPGA internal system
Fig. 3 is the internal structure of FPGA in the ultrasonic motor control driving circuit. The core of its design is the tailorable Nios II soft core and the DDS module that sends out the sinusoidal signal and the counting module that reads the feedback pulse of the grating encoder.
1.2.1 Construction of Nios Ⅱ system
Nios II is a soft-core 32-bit RISC microprocessor developed by Altera. As a soft-core written in hardware description language, Nios II can form Nios with other hardware interface modules described in HDL language through the built-in Avalon bus mechanism. The system is embedded together in Altera's Stratix, Cyclone or APEX series FPGAs to form a programmable system-on-chip design.
First of all, build a minimal system based on Nios II. The components of this system are all in the IP core provided by SOPC Builder. Select the Nios II processor, EPCS controller, SDR AM controller, and JTAG module in turn. Among them, Nios II realizes the function of MCU, SDRAM and EPCS controller components are used to connect external memory, JTAG module realizes the debugging and downloading of the program. In addition, we also need to use the serial port to receive the data sent by the host computer and the timer interrupt, so add a UART module and a timer module to the system. Finally, the processor needs to control the operation of the DDS module and receive the number of pulses calculated by the raster counting module, and some I/O ports need to be added for data transmission. In this way, a NIOS system inside the FPGA is built.
1.2.2 DDS module
Direct Digital Frequency Synthesizer (Direct Digital Frequency Synthesizer) is a frequency synthesis technology based on all-digital technology, which directly synthesizes the required waveform from the concept of phase. The basic principle is to generate sine wave, cosine wave, triangular wave, triangular wave, square wave and other waveforms with controllable frequency and phase in the form of numerical control oscillator. Figure 4 shows the basic structure of DDS.
In Fig. 4, fc is the clock frequency, K is the frequency control word, N is the word length of the phase accumulator, D is the ROM data line width.
The DDS design in this paper is mainly divided into three modules: the control word receiving module, which is used to communicate with the NIOS system and receive the control word from the host computer; the waveform memory module, which is used to generate the waveform required by the driving signal. This paper only needs to generate Sine wave; phase accumulator module, used to generate frequency and phase, this article is to convert the received frequency and phase control words into actual frequency and phase.
1.2.3 Pulse counting module
The pulse counting module consists of two parts: filtering and counting, mainly to read the information fed back by the grating encoder, so as to realize the precise positioning and speed control of the motor. The grating encoder used in this article has a resolution of 0.5um/count and outputs 2 differential signals of A+/A-, B+/B-. In order to convert the differential output of the encoder into a single-ended pulse signal, this article selects 26LS32AC differential Convert to single-ended chip to realize the conversion of differential signal. The converted two-way signals A and B are a set of orthogonal pulse signals. When the motor moves in different directions, the difference between the two-way signals A and B
The phase relationship of the motor will be reversed to determine the direction in which the motor is running. Therefore, according to this characteristic, in FPGA, a counting module that realizes the function of the quadrature encoding pulse circuit is programmed with Vetilog language.
At the same time, in order to further eliminate the narrow pulse interference signal that may be generated by the grating feedback signal, the controller further filters the converted single-ended signal. The main process is: when collecting a certain state signal, use a sampling clock with a higher frequency than the state signal to repeatedly collect it for many times, until the multiple collection results are completely consistent, it is regarded as a valid signal output. Then the filtered signal is sent to the quadrature encoder pulse circuit for direction identification and counting.
1.3 Control mode of drive controller
When the motor is working, the FPGA receives the data from the upper computer through the serial port and sends it to the Nios II processor. After program processing, the information such as the motor running mode (stepping, continuous), running distance, etc. is obtained, and the Nios II processor passes the control The start and stop time of the DDS module controls the presence or absence of the drive signal and then controls the movement process of the motor. The actual information of the displacement and speed of the motor during operation can be obtained from the feedback signal of the grating encoder. The counter module calculates the value of the pulse number and sends it to the Nios II processor. The processor changes the amplitude of the DDS output signal through a specific control algorithm. Value, frequency, phase to make further adjustments to the running state of the motor. In this way, a complete closed-loop control system is realized by an FPGA chip.
2 Experimental analysis
2.1 Research on speed stability of ultrasonic motor
Since the ultrasonic motor is within a certain frequency range, its speed decreases with the increase of the frequency, so we can ensure the stability of the ultrasonic motor speed by controlling the frequency of the sinusoidal signal.
The linear ultrasonic motor used in this experiment is relatively stable around 33.8 kHz, so 33.8 kHz is selected as the experimental frequency of the linear ultrasonic motor. First study the speed stability of the linear ultrasonic motor without adding any control algorithm. The experimental results are shown in Figure 5.
It can be seen from the above figure that the speed of the ultrasonic motor is not very stable when it is run directly without the control algorithm. If some control algorithms are added to the Nios II processor to control the frequency when the motor is running, the speed stability will be significantly improved. Take the incremental PID algorithm as an example:
△u(k)=A1e(k)+A2e(k-1)+A3e(k-2)
u(k) is the frequency, and e(k) is the difference between the target speed and the current speed at the Kth sampling time. Calculate the frequency change through the above formula, send a new frequency control word to the DDS module, and change the frequency of the drive signal, so as to achieve the effect of controlling the running speed of the motor. Figure 6 is the speed curve of the motor after adding the PID algorithm.
It can be seen that the speed fluctuation of the ultrasonic motor driven by the control algorithm is much smaller than the fluctuation of the linear ultrasonic motor without the algorithm. This well solves the problem of speed stability of the linear ultrasonic motor during motion.
2.2 Positioning accuracy test
Precise positioning experiments are carried out on a single-axis linear ultrasonic motor motion platform. This precision motion platform has relatively stable output characteristics when the pulse width is 3.5μs, and the step distance is about 100 nm. Use the "continuous + step" method for precision testing, continuously move to the predetermined target, and then use micro-steps to adjust. The XL-80 laser interferometer system of British REN-ISHAW company is used as the measurement system of this experiment, and the laser interferometer display data is compared with the positioning distance. Experiments show that the positioning accuracy of the ultrasonic motor linear motion platform can reach 1 μm.
3 Conclusion
In this paper, using SOPC technology , the waveform generation module, microprocessor module and pulse counting module are cleverly integrated into an FPGA, and the design of the ultrasonic motor drive control circuit is realized by using the flexibility of programmable logic and the powerful processing capability of Nios II . Using SOPC scheme for system design, making full use of the programmability of FPGA, the whole development process becomes flexible and convenient, and the software and hardware of the system can be upgraded without changing any peripheral circuits, prolonging the life cycle of the system, and greatly improving the The performance and integration of the system reduce the development cost of the system, which is the advantage over other solutions and also conforms to the development direction of today's science and technology.