IA-32 fixed-point arithmetic instructions

Common instructions for fixed-point arithmetic operations

–加 / 减运算（影响标志、不区分无/带符号）
ADD：加，包括addb、addw、addl等
SUB：减，包括subb、subw、subl等

–增1 / 减1运算（影响除CF以外的标志、不区分无/带符号）
INC：加，包括incb、incw、incl等
DEC：减，包括decb、decw、decl等

–取负运算（影响标志、若对0取负，则结果为0且CF清0，否则CF置1）
NEG：取负，包括negb、negw、negl等

–比较运算（做减法得到标志、不区分无/带符号）
CMP：比较，包括cmpb、cmpw、cmpl等

–乘 / 除运算（不影响标志、区分无/带符号）
MUL / IMUL：无符号乘 / 带符号乘
DIV/ IDIV：带无符号除 / 带符号除

Specific execution of fixed-point arithmetic instructions

Continue to use the add function in the previous section

• The function of lea here is the same as add %edx, %eax
  EIP=80483e0
  

• eax is register 0 of the general register
  edx is register 2 of the general register
  IR=8d040289

• After decoding, it is known that the function R[eax]<-R[edx]+R[eax]*1
  sends two registers to the ALU for calculation

• Recall: What are the components of the ALU as shown in the figure below
  Complementary adder/subtractor
  Logical operation unit
  Multiplier? No divider? None
  Multiplication/division can be implemented with addition, subtraction + shift, or separate multipliers/dividers. Signed
  multiplication and unsigned multiplication are independent units.
  Signed division and unsigned division are independent units.
  

• Complementary code adder and subtractor:
  
  - After the ALU operation is completed, the flag information is sent to the flag register, and the adder selection output is sent back to the No. 0 register through the multiplexer, and the No. 0 register is 80000001. The calculation and overflow of positive and negative
  
  complements No longer

Multiplication and division instructions

• Multiplication instruction: One, two or three operands can be given
  – if one operand SRC is given, the other source operand is implied in AL/AX/EAX, multiplying SRC and the contents of the accumulator, and the result Stored in AX (16-bit) or DX-AX (32-bit) or EDX-EAX (64-bit). DX-AX means that the high and low 16 bits of the 32-bit product are in DX and AX respectively.
  n bits × n bits = 2n bits
  – If two operands DST and SRC are given in the instruction, then DST and SRC are multiplied and the result is in DST.
  n bits × n bits = n bits
  – If three operands REG, SRC, and IMM are given in the instruction, multiply SRC and the immediate IMM, and the result is in REG.
  n bits × n bits = n bits
• Division instruction: only clearly indicate the divisor, divide by the specified divisor by the content in EDX-EAX
  – if it is 8 bits, then the 16-bit dividend is in the AX register, the quotient is sent back to AL, and the remainder is in AH
  – if it is 16 bits, then 32 The digit dividend is in the DX-AX register, the quotient is sent back to AX, and the remainder is in DX
  – if it is 32 bits, the dividend is in the EDX-EAX register, the quotient is sent to EAX, and the remainder is in EDX

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Reference: NTU Computer System Fundamentals (1)