1, fixed-point and floating-point
Decimal point in the calculator and no special device for storage. The position of the decimal point is fixed or digital can be divided into fixed-point and floating-point numbers .
Fixed point
Fixed-point decimal point position of the fixed number of decimal point position by prior agreement . The same fixed-point machine code, each of the weights are the same.
Agreed after the decimal point in the value of the lowest bit fixed point called fixed pure integer ; is called before the highest value bit fixed-point decimal fraction . Using a machine called a fixed point pointing machine .
Encoding provided 8, wherein the highest bit is the sign bit .
For the fixed-point integer machine :
the original code and the inverted value range: -2 . 7 + 1 ~ 2 . 7 - a
numerical ranges complement: -2 . 7 ~ 2 . 7 - 1
for fractional fixed point machine :
the original code and the inverted value range: -1 +2 -7 to 1 - 2 -7
numerical ranges complement: -1 to 1 - 2 -7
When the fixed-point value exceeds the range that can be expressed, called overflow .
Float
Floating decimal point position is not a fixed number.
Floating-point in the computer consists of two parts: exponent and mantissa .
Wherein the mantissa represents a valid number values, order code indicates the position of the decimal point.
For common exponent k + 1 bit mantissa total of n + 1 -bit floating point (including symbols each):
the maximum positive number : (. 1 - 2 -n ) * 2 2-K ^. 1
Minimum negative : -1 * 2 2 ^ k 1-
absolute value of the minimum number (other than 0): ± 2 -n * 2 -2 ^ K
Exponent and mantissa are complement representation.
Normalized floating-point number
Since the numerical value can have a plurality of different floating-point number to be expressed, to regulate the value of the representation, should be constrained to certain conditions, referred to as a normalized floating point number .
Normalized floating-point constraints : For the mantissa M, should be 0.5 ≤ | M | ≤. 1 .
For the original code, which is a maximum value of a certain bit.
For complement, which is the highest value of the sign bit and different from each.
IEEE-754 standard
IEEE-754 standard defines three kinds of basic format floating point numbers: single precision format , double format , extended-precision format .
For single precision and double-precision formats, IEEE-754 standard specifies an implied decimal point left, as integer digits. The predetermined bit is 1, need not be stored, automatically calculated. Since the hidden position on the bits, compared to the standard of a normalized floating-point number to the left, so exponent -1 need to match.
Single format : order code is 8 bits, the mantissa value is 23 bits, a total 32 bit
double format : order code is 11 bits, the mantissa value is 52 bits, the total 64-bit
extended precision format : exponent bits 15, the median value of the mantissa is 64, the total 80
Since the implied bit mantissa mantissa actual single-precision and double-precision formats 24 and 53, respectively.
For single precision format, exponent of the range is -126 to 127.
This place is what I do not understand it. After find information personal understanding is: full order code 0 and all-1 is a special case; 0 corresponding to a full complement is 10000001, -127, corresponding to all 1's complement is 10000000 -128. So these two values should be excluded. See from the bias constant, and the -127 to -128 offset 0 and -1, machine code can not be represented by 8.
IEEE-754 standard floating-point equation : V = (-1) MS * 2 2 ^ 127-E * M
decimal precision to single steps of: 1) a binary switch 2) normalized 3) Find the exponent 4) spliced 5) * Four transfer hexadecimal
single decimal precision rotation steps of: 1) a split four turn binary * 2) segment 3) find the original code symbol order 4) true value is calculated
2, check code
Accessing data transfer process, the external high-frequency interference due to intermittent failure of equipment, power transients and other accidental error occurs. To reduce such errors, in addition to improving the reliability of the hardware itself, but usually by adding some redundancy , legitimate data encoding some errors , called illegal code , to detect errors. Code distance is between any two mutually different coded bits. Code distance of only 2 check code having the error correction capability.
Parity
Together with a valid check code information, may be formed parity . This is the simplest kind of check code.
Odd : adding check bits , the check code is a 1 bit number is odd. ~ C = x1 ⊕ x2 ⊕ ... ⊕ xn ( odd number and have any number of 0 XOR 1; 1 to give an even number of 0)
even parity : adding check bits , the check code is a 1 bit number is an even number . C = x1 ⊕ x2 ⊕ ... ⊕ xn
parity check an error can, but can not determine the location of the error.
Hamming check code
Hamming check code is capable of locating an error , and can find two error check code, and can restore a syndrome check code.
Provided a total effective symbol k bits, parity bits r total, if desired, a positioning error, there Hamming inequality. 1 : 2 r ≥ k + r +. 1; (k + r bits may be wrong, the case with the right)
If two errors need to check further, there Hamming inequality 2 : 2 R & lt-. 1 ≥ K + R & lt. (2 requires otherwise indicates an error)
Hamming code check code encoding rules :
- Hamming check code provided MSB is m, the lowest bit is 1, the Hamming check code can be expressed as: H (m) H (m-1) ... H (1) ;
wherein, H (2 I-1 ) occupied by the check bits R (i), from small to large remaining positions occupied by the effective symbol K (i); if the presence of H (2 I-. 1 ), then R (i) occupying the highest position.
For example thirteen Hamming code parity (parity bit five, eight effective symbol): R (5) K ( 8) K (7) K (6) K (5) R (4) K (4 ) K (3) K (2 ) R (3) K (1) R (2) R (1) - Hamming checksum every bit number, equal to test his parity bit and the number. For example, H (3): 3 = 2 + 1; thus H (3) (1) check the H (2) and H. Each bit corresponds to a parity, are the effective parity check code thereof .
Significant bit must equal the parity bit number and bit number; parity bit number is equal to the sum of itself.
- Even parity to an example, equations can be obtained:
Pl = Dl D2 of ⊕ ⊕ ⊕ D7 D5 D4 ⊕
P2 = ⊕ Dl D4 D3 ⊕ ⊕ ⊕ D7 D6
P3 D3 = D2 of ⊕ ⊕ ⊕ D8 D4
P4 D5 = D6 ⊕ ⊕ D7 D8 ⊕
P5 Dl = D2 of ⊕ ⊕ ⊕ D3 D4 D5 ⊕ ⊕ ⊕ D6 D7 D8 ⊕ ⊕ ⊕ Pl P2 P3 ⊕ ⊕ P4 (the highest order bits equal to or exclusive of all other Hamming code)
by using the equations can be formed Hamming check code.
Error detection , the parity bit and so need to check the checksum XOR operation equations can be obtained:
Sl = Pl ⊕ D2 of Dl ⊕ ⊕ ⊕ D7 D5 D4 ⊕
S2 = P2 Dl ⊕ ⊕ ⊕ D3 D4 D6 ⊕ ⊕ D7
S3 = P3 ⊕ D2 of ⊕ D3 ⊕ D4 ⊕ D8
S4 = P4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D8
S5 = P5 ⊕ Dl ⊕ D2 of ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D8 ⊕ Pl ⊕ P2 ⊕ P3 ⊕ P4
obviously, if this bit is not error , and is equivalent to their own XOR operation, the result must be kept zero ;
the other hand, if a check result is a 1 , indicating that the data error check bits .
When considering only one error and two errors, the following situations:
. 1, Sl ~ S5 are all zero : error data;
2, S5 = 0; Sl ~ S4 are zeroes : Two error;
3, S5 = 1; S1 ~ S4 are all 0 : P5 error;
. 4, S5 = 1; S1 ~ S4 is only a 1 : that a corresponding error check bits; as S1 = 1, P1 described error;
5,S5 = 1; S1 ~ S4 is more than 1 : Common test element S by the error, the positioning error location; if S1, S2 = 1, D1 described error.
Cyclic redundancy code (CRC code)
CRC code may be multi-bit error detected and corrected during storage or transport of consecutive, so widely used between the magnetic storage medium, and computer communications.
The CRC code from the k-bit information symbols followed by r bits Parity composed by 2 operation mode rule.
CRC code encoding rules :
- The information code expressed as a polynomial M (X) = X *. 1 Ck- K-. 1 + ... + a C1 * X . 1 + C0;
- The information code of r bits to the left, to give M (X) * X r = X *. 1 Ck- K +. 1-r + ... + C0 * X r ;
- With M (X) * X R & lt divided by the generator polynomial for G (x), the remainder obtained as a parity bit. In order to check code is r bits, can be seen from the operated modular law 2, G (x) will be for the r + 1 bit.
- Provided the step of calculating the quotient is Q (x), the resulting remainder is R (x), the R (x) spliced to M (X) * X r on the right vacated r bits constituting the information is a CRC code .
The CRC code M (X) * X R & lt + R & lt (X) = [Q (X) * G (X) + R & lt (X)] + R & lt (X) = Q (X) * G (X) + 2R ( x);
additions by die 2, 2R (x) should be 0; therefore the formula = Q (x) * G ( x), i.e. the CRC code will be G (x) divisible.
Error detection , the CRC code obtained by dividing the generator polynomial G (x), if no error occurred, the remainder should be 0; different bit error, a different residue. It can be shown in the code system and generator polynomial invariant, with the remainder offset relationship is unchanged.
