Today I want to share with you the interface MII between MAC and PHY.
MII (Media Independent Interface) is a media independent interface. The MII interface defines the interface for transmitting information such as data and control status between the MAC layer and the physical layer. It is a 10M and 100M compatible interface. After expansion, it can also be used for the interface between the MAC layer and the physical layer of 1000M (GMII interface ).
1. Personal experience exchange
After throwing out this definition, I want to talk to you about the process of knowing this interface at that time.
First of all, my direction is embedded software, such commonly used PHY chips, such as 88e1111, DP83848, etc., have corresponding driver support under uboot and linux, and developers do not need to care. And they all use basic network communication functions. For some complex PHY chips such as XL53XXX with 1588 functions, manufacturers need to provide related drivers, which include configuration of some special registers and related API interfaces.
On the premise that software engineers don't care about it, it is necessary to ensure that the hardware principle design and pcb design are no problem. In actual engineering applications, if it is not an iterative product, there is a high probability of problems with newly developed boards. Under this premise, I also have a deeper understanding of PHY and hardware-related knowledge.
The MII interface is used between the MAC and the PHY. Search for MII on the Internet, and various mii detailed explanations (mii-gmii-rgmii-rmii-smii-ssmii-tbi-rtbi-rtbi-xgmii-xaui-xlaui, etc.) come out. faint. I read some other materials later, and learned about the commonly used PHY interfaces. There are four commonly used types: MII, RMII, GMII, and SGMII.
As mentioned above:
The internal MAC peripherals will be connected to the external PHY chip through the corresponding interface. According to the different data transmission modes, it can be roughly
into the following two categories:
⚫ MII/RMII interface: Support 10Mbit/s and 100Mbit/s data transmission mode;
⚫ GMII/RGMII interface: support 10Mbit/s, 100Mbit/s and 1000Mbit/s data transmission mode.
Which interface the chip supports will be mentioned in the PHY chip manual.
The following figure is the interface description of the 88e1111 manual:
The following figure is the interface description of the DP83848 manual:
88e1111 is Gigabit PHY, and DP83848 is 100M PHY. The MAC on the zynq ps side only supports RGMII. If emio is used, the GMII interface will come out. If you want to change to other interfaces, you can use the IP core to convert GMII to XXXX. Therefore, attention should be paid to the selection of PHY and hardware design.
The information related to MII on the Internet is relatively complete, and the author also extracts the following content to improve the structure of this article.
2, MII connector
The full name of MII is Media Independent Interface, which literally translates to Media Independent Interface. It is an Ethernet standard interface defined by IEEE-802.3. The MII interface is used to connect the Ethernet MAC to the PHY chip. The connection diagram is shown in the following figure:
There are a total of 16 signal lines in the MII interface, the meanings are as follows:
TX_CLK: Send clock, if the network speed is 100M, the clock frequency is 25MHz, and if the network speed is 10M, the clock frequency is 2.5MHz, this clock is generated by PHY and sent to MAC.
TX_EN: Transmit enable signal.
TX_ER: Send error signal, active high, indicating that the data transmitted within the valid period of TX_ER is invalid. TX_ER does not work at 10Mpbs network speed.
TXD[3:0]: Send data signal lines, a total of 4 lines.
RXD[3:0]: Receive data signal lines, a total of 4 lines.
RX_CLK: Receive the clock signal. If the network speed is 100M, the clock frequency is 25MHz, and if the network speed is 10M, the clock frequency is 2.5MHz. RX_CLK is also generated by the PHY.
RX_ER: Receive error signal, active high, indicating that the data transmitted within the valid period of RX_ER is invalid. RX_ER does not work at 10Mpbs network speed.
RX_DV: Receive data is valid, similar to TX_EN.
CRS: Carrier Sense Signal.
COL: Collision detection signal.
The disadvantage of the MII interface is that too many signal lines are required, not counting the data lines of the two management interfaces, MDIO and MDC, so the use of the MII interface has become less and less.
3. RMII interface
The full name of RMII is Reduced Media Independent Interface, which translates to a simplified media independent interface, which is a simplified version of the MII interface. The RMII interface only needs 7 data lines, which is directly reduced by 9 compared with the MII, which greatly facilitates the wiring of the board. The schematic diagram of the RMII interface connected to the PHY chip is shown in the figure below:
TX_EN: Transmit enable signal.
TXD[1:0]: Send data signal lines, a total of 2 lines.
RXD[1:0]: Receive data signal lines, 2 in total.
CRS_DV: Equivalent to the mixing of the two signals RX_DV and CRS in the MII interface.
REF_CLK: Reference clock, provided by an external clock source, the frequency is 50MHz. Different from MII here, the receive and transmit clocks of MII are separated independently, and both are provided by the PHY chip.
4. GMII interface
GMII (Gigabit Media Independant Interface), gigabit MII interface. GMII adopts 8-bit interface data, and the working clock is 125MHz, so the transmission rate can reach 1000Mbps; meanwhile, it is compatible with the 10/100Mbps working mode stipulated by MII. The data structure of the GMII interface conforms to the IEEE Ethernet standard, and the definition of the interface can be found in IEEE 802.3-2000. The signal definition is as follows:
GTX_CLK: Transmit clock (125MHz) in 1000M working mode.
TX_EN: Transmit enable signal.
TX_ER: Send error signal, active high, indicating that the data transmitted within the valid period of TX_ER is invalid.
TXD[7:0]: Send data signal lines, a total of 8 lines.
RXD[7:0]: Receive data signal lines, a total of 8 lines.
RX_CLK: Receive clock signal.
RX_ER: Receive error signal, active high, indicating that the data transmitted within the valid period of RX_ER is invalid.
RX_DV: Receive data is valid, similar to TX_EN.
CRS: Carrier Sense Signal.
COL: Collision detection signal.
Compared with the MII interface, the data width of GMII changes from 4 bits to 8 bits. The functions of the control signals in the GMII interface such as TX_ER, TX_EN, RX_ER, RX_DV, CRS and COL are the same as those in the MII interface. The sending reference clock GTX_CLK and The frequency of the receiving reference clock RX_CLK is 125MHz (in 1000Mbps working mode). There is one point that needs to be specially explained here, that is to send the reference clock GTX_CLK, which is different from the TX_CLK in the MII interface. The TX_CLK in the MII interface is provided by the PHY chip to the MAC chip, while the GTX_CLK in the GMII interface is provided by the The directions provided by the MAC chip to the PHY chip are different. In practical applications, most GMII interfaces are compatible with MII interfaces, so general GMII interfaces have two transmission reference clocks: TX_CLK and GTX_CLK (the directions of the two are different, as mentioned above) , when used as MII mode, use TX_CLK and 4 of the 8 data lines.
5. RGMII interface
RGMII (Reduced Gigabit Media Independant Interface), a simplified version of the GMII interface. Reduce the number of interface signal lines from 24 to 14 (COL/CRS port status indication signal, not shown here), the clock frequency is still 125MHz, and the TX/RX data width is changed from 8 to 4 bits, in order to maintain the 1000Mbps The transmission rate remains unchanged, the RGMII interface samples data on both the rising and falling edges of the clock, and sends TXD[3:0]/RXD[3:0] in the GMII interface on the rising edge of the reference clock, and transmits TXD[3:0]/RXD[3:0] on the falling edge of the reference clock Transmit TXD[7:4]/RXD[7:4] in GMII interface. RGMII is also compatible with two rates of 100Mbps and 10Mbps, and the reference clock rates are 25MHz and 2.5MHz respectively. The TX_EN signal line transmits two kinds of information, TX_EN and TX_ER, and sends TX_EN on the rising edge of TX_CLK, and sends TX_ER on the falling edge; similarly, the RX_DV signal line also transmits two kinds of information, RX_DV and RX_ER, and sends RX_DV on the rising edge of RX_CLK, and sends RX_DV on the falling edge of RX_CLK. along send RX_ER. The RGMII interface definition is as follows:
Please correct me if there is any mistake! Next time I want to talk about MDIO, and I hope to make progress together with you!