bus control
After reading the articles on the Internet, the quality is really not good, so I combined it myself to sort it out.
Bus control mainly includes two aspects, bus arbitration control and bus communication control .
1. Bus Arbitration Control
Only one device is allowed to occupy the bus at the same time. In order to prevent conflicts, we have introduced arbitration logic to arbitrate who can occupy first.
(In fact, I didn't expect that the queuer was not proposed here, and the queuer should go to the IO interrupt.)
There are three centralized modes of bus arbitration control: chain query, counter timing query, and independent request mode.
1. Chain query method
It's actually the easiest way. Control via three unidirectional signals.
The basic process is also from top to bottom.
| Signal (I choose the English name casually) | describe | The control signal goes through the control bus |
|---|---|---|
| BR (Bus Request) | bus request application | Multiple devices share a bus application line (a control bus), and when the bus needs to be occupied, an application signal is sent to this line. |
| BG (Bus Grant) | bus allowed | When the bus control device receives the BR signal, it sends out the BG signal from the BG line. But the decision of this priority is determined by the BG line. The BG line is similar to a chain structure. Only after passing the previous one can the next one be reached. When the signal reaches the device in need, it is intercepted. So the closest to the bus will have high priority. |
| BS (Bus Suspend) | bus busy | After intercepting the BG signal, the device sends a BS signal to the bus device controller, indicating that the matching is successful. |
Note: The component closest to the bus controller in the query chain has the highest priority, and the farther away from the bus controller, the lower the priority.
Chain query is implemented through the priority queuing circuit of the interface.
Advantages: simple structure, mainly used in simple embedded systems
Disadvantages: slow speed, need to keep checking down, especially sensitive to circuit failure
2. Counter timing query method:
In fact, it is a polling idea, which is a bit similar to the Clock algorithm.
Removed the BG line, added a set of device address lines ( LogNstrips, in order to cover all addresses)
The same as the early process of the chain query, the request is sent when there is a need, and the BS signal is sent when the match is successful.
But the matching method has changed. Now it scans according to the address of the device , that is, a counter (digital power PTSD) is added inside the controller . Recall what the counter is for. It is a traversal of numbers one by one, binary form output to our device address line.
That is to say, the controller has been reporting to the outside no matter what happens outside.
If an external device that wants to occupy the bus is called by its name at this time, it will immediately respond to the controller (BS signal), and then it will be occupied.
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Note: The initial value of the counter can be set by the program to change the priority order conveniently. Of course, this flexibility comes at the cost of increasing the number of control lines.
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If the initial value of the counter starts from 0, the priority order of each component is the same as the chain query method.
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If starting at the point where it left off, each device has equal priority in using the bus
3. Independent request method
This is the most extravagant way. Each device is connected to a BR and BG, and then we can go directly to the queue. Or it can be controlled by software.
2. Bus communication control
The bus communication control is mainly responsible for managing when the two parties start communicating and when it ends.
bus cycle
The time to complete a bus operation is usually called a bus cycle.
| stage | |
|---|---|
| Application for allocation stage | That is, our main device sends a request, arbitrates, and whether to get the right to use |
| addressing phase | The master device that has obtained the right to use, sends out the address and information, and starts our slave device |
| pass phase | data exchange phase |
| end stage | Withdraw the main module |
Let's talk about our four ways
synchronous communication
The main feature of synchronous communication is that our master and slave devices use the same time scale (same CP) .
- The main module needs to occupy the bus to issue commands
- Prepare data from the module without occupying the bus
- Send data from the module to occupy the bus
In synchronous mode, the read operation process:
- On the rising edge of the first clock cycle, the CPU issues the address.
- On the rising edge to the second clock cycle, the CPU issues a read command.
- On the rising edge of the third clock cycle, the memory will address internally and send the data in the storage unit to the data bus.
- The CPU is well aware of the working speed of the memory. After one clock cycle, the CPU samples on the data bus and fetches the data. The memory cancels the data signal on the data bus, and the CPU cancels the read signal on the control bus.
- To ensure that the data is transmitted correctly, the address information must be kept on the address bus for one more cycle , and finally the address information will be revoked on the address bus, thus passing a complete fourth clock cycle.
In synchronous mode, the write operation process:
- On the rising edge of T1, the CPU sends address information;
- On the falling edge to T1, the CPU sends data to the data bus.
- Then on the rising edge of T2, the CPU sends a write command signal. At this time, the memory knows that the CPU wants to write a data into the memory, so it takes the address information to be written from the address bus, takes the data from the data bus, and writes the data Write to the specified memory location.
- This process lasted for quite a long time, after two clock cycles of T2 and T3, after writing, the CPU cancels the data information of the data bus and the write signal of the control bus.
- In order to ensure that the data can be completely written into the memory, the address information must be kept on the address bus for one more clock cycle . Finally, the address information on the address bus is withdrawn.
asynchronous communication
Asynchronous communication overcomes the shortcomings of synchronous communication, allows the speed of each module to be inconsistent, and gives designers sufficient flexibility and choice. It does not have a common clock standard, and does not require strict uniform operation time of all components, but adopts a response method (also known as a handshake method) , that is, when the master module sends a request signal, it waits for the "response" signal fed back from the slave module before starting Start communication. This requires two additional acknowledgment lines between the master and slave modules .
Asynchronous communication, also known as response communication, is a communication method based on response or interlock mechanism. That is, the moment at which the latter event appears on the bus depends on the occurrence of the previous event . In such a system, no unified common clock signal is required, the length of the bus cycle is variable, no response time is imposed on the functional parts, thus allowing both fast and slow functional parts to be connected to the same bus, But this comes at the cost of increased bus complexity and cost.
In asynchronous communication, according to whether the response signal is interlocked, that is, whether the establishment and cancellation of the request and response signals depend on each other , asynchronous communication can be divided into three types: non-interlocked communication, semi-interlocked communication and full interlocked communication.
not interlocked
- After the master module sends out the request signal, it does not need to wait for the response signal from the slave module, but after a period of time, after confirming that the slave module has received the request signal, it cancels its request signal;
- After the slave module receives the request signal, it sends a reply signal when the conditions permit, and after a period of time (the setting of this period is different for different devices) after confirming that the master module has received the reply signal, it automatically cancels the reply signal.
- It can be seen that there is no interlocking relationship between the two communicating parties.
Semi-interlock (one handshake)
- When the master module sends out a request signal, it must wait for the response signal from the slave module to revoke its request signal, or the interlock relationship;
- The slave module sends a response signal after receiving the request signal, but it does not have to wait to know that the request of the Nerubian has been cancelled, but automatically cancels its response signal after a period of time, and there is no interlocking relationship.
- Since one side has an interlocking relationship and the other side does not, it is called a semi-interlocking method.
Full interlock (secondary handshake)
- The master module sends a request signal, and the request signal must be revoked after the slave module responds;
- When the slave module sends a reply signal, it must wait until it knows that the request signal of the master module has been revoked, and then revoke its reply signal.
- There is an interlocking relationship between the two engines, so it is called the full interlocking method.
semi-synchronous communication
Semi-synchronous communication integrates the advantages of synchronous and asynchronous communication, and not only retains the basic characteristics of synchronous communication, such as the sending time of all addresses, commands, and data signals, it starts strictly with reference to a leading edge of the system clock, and the receiver uses the system The timing of the trailing edge of the clock is used to judge and identify. At the same time, like asynchronous communication, it allows modules of different speeds to work harmoniously. A "wait" response signal line is added for this purpose.
Take the read command as an example. In synchronous communication, the master module sends out the address at T1, sends out the command at T2, transmits the data at T3, and ends the transmission at T4.
If the working speed of the slave module is slow and cannot provide data at T3, the master module must be notified before T3 to enter the waiting state. At this moment, the slave module is set to be active at low level.
When the main module detects that "waiting" is valid at T3, it does not immediately take data from the data line, and waits for one clock cycle and one clock cycle until the main module detects that the "waiting" is at a high level, that is, when the waiting is invalid, the main module immediately puts The next cycle at this moment is regarded as the normal cycle T3, and the data is acquired immediately, and the transmission ends at T4.
The semi-synchronous communication timing can be:
- T1 master module sends address;
- T2 main module sends commands;
- When Tw is active at low level, it enters waiting, and its interval is the same as T;
- When Tw is active at low level, it enters waiting, and its interval is the same as T;
- ……
- T3 provides data from the module (if it is a read command);
- T4 Withdraws data from the module.
Semi-synchronous communication is suitable for a simple system that does not have a high working speed but includes many devices with different working speeds. The semi-synchronous communication control method is simpler than the asynchronous communication, and all modules in the whole system work synchronously under the control of a unified system clock, with high reliability and convenient synchronous structure. Its disadvantage is that the system clock frequency cannot be too high, so overall, the system work speed is still not very high.
Summary: The core of semi-synchronous communication is to add a waiting line (because the preparation process of the slave module may be slow and take several cycles), if it is not ready, the master module will wait for the slave module, but according to the cycle as the step size .
split communication
Synchronous communication, asynchronous communication and semi-synchronous communication all start from the master module sending address and read and write commands until the end of data transmission. During the entire transmission cycle, the right to use the system bus is completely occupied by the master module that has the right to use and the slave module selected by him. Further analysis of the read command transmission cycle shows that except for the stage of applying for the bus, the rest of the time is mainly spent in the following three aspects.
- 1. The master module sends addresses and commands to the slave module through the transmission bus.
- 2. The slave module makes necessary preparations for reading data according to the command.
- 3. The slave module provides data to the master module through the data line.
For the system bus, there is no substantial information transmission in the process of reading data from the inside of the module, and the bus is purely idle waiting.
In order to overcome and take advantage of this passive waiting, especially in large-scale computer systems, the load of the bus is already in a saturated state, fully exploiting the potential of the system bus at every moment will play a great role in improving the system performance.
To this end, a "separated" communication method is proposed.
Basic idea: to decompose a transmission cycle (or bus cycle) into two sub-cycles.
In the first sub-cycle, the main module A sends commands, addresses and other related information, including the main module number (this number is especially important when there are multiple main modules) to the system bus after obtaining the right to use the bus. After being transmitted by the bus, it is received by the relevant slave module B.
The main module A releases these information to the system bus and only occupies the bus for a short time. Once the sending is completed, it immediately gives up the right to use the bus so that other modules can use it.
In the second sub-cycle, when module B receives the relevant command signal sent by module A, after a series of internal operations such as selection, decoding, and reading, the data required by module A is prepared, and then module B Apply for the right to use the bus. Once approved, the B module will send a series of information such as the number of the A module, the address of the B module, and the data required by the A module to the bus for the A module to receive. Obviously, the above two sub-cycles have only one-way information flow, and each module becomes the main module.
The characteristics of this communication method are as follows:
- 1. Each module must apply for the right to use the bus.
- 2. After obtaining the right to use the bus, the main module sends information to the other party within a limited time, and transmits in a synchronous manner, without waiting for the reply signal from the other party.
- 3. Each module does not occupy the bus in the process of preparing data, and the bus can accept requests from other modules.
- 4. When the bus is occupied, it is doing effective work, or through it to send commands, or through it to transmit data, there is no idle waiting time, and the effective occupation of the bus is fully utilized, thus realizing multiple master and slave modules. It is extremely important for large-scale computers to carry out cross-overlapped parallel transmission.
This method is more complicated to control, and is rarely used in ordinary microcomputer systems.