UVM is a unified verification method, which is very important. Many people are developing in the direction of IC verification, and they will learn about UVM more or less. For verification engineers, mastering UVM can greatly reduce the difficulty of verification engineers working across companies and projects.
UVM
Universal Verification Methodology (UVM) is a verification platform development framework based on the SystemVerilog class library. Verification engineers can use its reusable components to build a functional verification environment with a standardized hierarchy and interface.
UVM TEST
UVM TEST is the top-level Component of UVM. It mainly completes the instantiation and configuration of the top-level env, and generates incentives through the env call sequence to give to the DUT.
In general, there will be a basic base_test for env instantiation and other common UVM element component generation instantiation. Then other tests inherit the base_test and configure env in a targeted manner or choose a different sequence to test.
UVM Environment
UVM env is mainly used to associate UVM components with layers. Generally, the agent and scoreboard are instantiated in env, and the settings are other envs. The top-level env is used to encapsulate the environment used to test the DUT.
UVM Scoreboard
Scb is mainly used to check whether the behavior function of DUT is as expected. The transaction of input and output of DUT is received through the analysis port of agent. Inject the input transaction into the reference model to produce the expected result, and then compare it with the actual output result of the DUT.
UVM Agent
The agent is used to layer and connect some UVM components, mainly used to complete the DUT interface.
A typical agent includes a sequencer for managing the stimulus sequence, a driver for applying stimulus to the DUT interface, and a monitor for monitoring the DUT interface, and may also include some such as coverage collection, protocol inspection, etc. The agent can work in two modes: active and passive. The former is used to generate incentives, while the latter is only for monitoring interfaces and does not have control capabilities.
UVM Sequencer
The sequencer is used to select the control transaction sequence from the sequence, similar to an arbiter. Simply put, it is mainly used to control transactions.
UVM Sequence
sequence is the object used to generate incentives.
UVM Driver
The driver obtains the sequence of the transaction from the sequencer and drives it to the interface of the DUT, which is accomplished by using the TLM port here. This involves converting abstraction layer data into specific port signals.
UVM Monitor
The monitor samples the DUT interface signals and sends them to other components of the verification platform for analysis. Similar to driver, it also involves the conversion of abstract data and concrete data. In order to realize the above functions, usually the monitor has an interface for accessing the DUT and broadcasts the generated transaction through the TLM analysis port. The monitor can do some processing on the generated transactions internally, such as coverage collection, inspection, logging, etc., or these transactions can be processed by a dedicated component.