[Literature Reading] Research and Design of 1GHz Broadband Low Noise Analog Channel_Zeng Honglin

Design specifications

Signal Conditioning Channel

overall gain

Conditioning overall scheme block diagram

3.1 Noise of Cascode Amplifiers

3.1.1 Common types of operational amplifier noise
Thermal noise of resistors
1/f noise
White noise
3.1.2 Operational amplifier noise
Operational amplifier equivalent input noise model
Operational amplifier noise calculation
3.1.3 Multi-stage amplifier cascade noise calculation
Noise figure
cascade Amplifier Noise Figure
Cascaded Amplifier Noise Calculations

Passive Attenuation Circuit Design

50Ω impedance attenuation network, choose π-type attenuation network, the attenuation multiple is 10 times.
1MΩ impedance attenuation network, the attenuation multiple is 50 times.

Design of Broadband Impedance Transformation Circuit

An impedance conversion circuit based on high and low frequency separation paths is designed using discrete components such as operational amplifiers, high frequency field effect transistors, and high frequency transistors.

There are detailed formula derivation. structural analysis.
The ADA4610 of ADI Company was chosen as the operational amplifier of the impedance transformation circuit.
Low noise figure high frequency triode ALG625, its characteristic frequency is as high as 25GHz, the maximum collector circuit height is 30mA, and the noise figure is 1.2dB.
ATA28143 is selected as the field effect tube, its bandwidth is as high as 10GHz, and the noise figure at 2GHz bandwidth is only 0.4dB.

Bias circuit design

The AD5568 precision of the analog-to-digital converter used in the design is 16 bits, the reference reference is 4.096V, and its minimum adjustment step is 0.0625mV.

The calculation of the bias is described in detail.

Analysis and Design of Low Noise Variable Gain Amplifier Circuit

Variable Gain Amplifier Circuit Structure

The variation range of the gain of the variable gain amplifier circuit is: -4.5 (38-42.5dB) ~38dB.

Fixed Gain Amplifier Circuit Design

The ALH2402 and ALH2401 operational amplifiers are selected, and the bandwidth reaches 1.8GHz and 2.4GHz respectively, and
the AEP4370 digital step attenuator is selected. The minimum attenuation step of AEP4370 is 0.25dB, the maximum attenuation range of a single chip is -31.75dB, the input signal bandwidth can reach 6GHz, and the attenuation control can be completed through the SPI interface.

ADC drive circuit design

(1) Input impedance design (2) Bandwidth and slew rate (3) Noise, harmonic distortion (4) Power supply design.
ALH3202 is selected as the ADC driver. The frequency response of the ALH3202 is very flat from DC to 2GHz, and the flatness in the 2GHz band is less than 0.5dB. The equivalent input noise is only 1.4nV/ Hz, and the noise figure in the 1GHz bandwidth is only 9dB.
The gain requirement of the ADC driving circuit is 20dB, so the gain of the single-stage ALH3202 amplifier circuit cannot meet the demand, so this design adopts the method of cascading two-stage ALH3202

Noise of Variable Gain Amplifier Circuit

3.4.4.1 Noise analysis of variable gain amplifier circuit
3.4.4.2 Noise simulation of variable gain amplifier circuit

3.5 Signal Conditioning Channel Low Noise Design

3.5.1 Power supply design
3.5.2 Filter design
3.5.3 Shielding and anti-interference design

3.6 Design of signal conditioning channel gain temperature compensation

Research and Design of Trigger Conditioning Channel

Trigger channel structure diagram

The amplitude of the signal entering the trigger selection from the signal conditioning channel is about 100mVpp at most, and the trigger signal entering the comparator is usually adjusted to about 1Vpp.
The fixed gain amplifier uses ALH2401 , the bandwidth reaches 2.4GHz, which meets the design requirements.

Trigger source selection circuit design

The 5:1 selector in this design is implemented by using a combination of a 4:1 selector AEP42350 and a 2:1 selector AEP4245.

Edge Trigger Circuit Design

The core of edge trigger circuit is the design of high-speed comparator circuit and trigger level adjustment circuit .
High-speed comparator : use Texas Instruments (TI) LMH7322 dual comparator , the rise time of the comparator is 160ps (equivalent bandwidth exceeds 2GHz), the output is compatible with the LVDS level standard, and the input level range is Vcc-1.5V~Vee , adjustable hysteresis voltage range, better meet the requirements of this design.

The trigger level outputs a voltage of 0-4.096V through the digital-to-analog conversion device AD5568, so
the trigger level cannot cover the voltage range of -500mV~0mV. Shifts the DAC output level towards the negative terminal.

Vcomp_level is -2.096~2V, which covers the ±500mV amplitude range of the trigger signal.

Frequency division circuit design

Usually the differential input LVDS interface of FPGA is difficult to receive digital signals exceeding 600MHz, but this time the trigger bandwidth of the analog channel is as high as 1GHz. The design adopts even frequency division. Since the rising edge and falling edge of the signal after even frequency division correspond to the rising edge of the original signal, a corresponding trigger edge selection
module is added to the trigger channel. SY58012 from MICREL Company is selected as

the 1:2 differential fan-out device , its maximum working bandwidth is 5GHz, and the input interface can be conveniently compatible with three level standards (LVPECL, LVDS, CML) through a special port interface. The 2:1 differential selector uses SY58018 with a maximum working bandwidth of 4GHz. The frequency divider is SY89875U , the working bandwidth is up to 2GHz, the differential LVDS level standard output, and the programmable frequency division ratio is: 1, 2, 4, 8, 16.

Trigger coupling circuit design

The trigger coupling circuit design mainly includes: trigger low frequency suppression, high frequency suppression, AC coupling and DC coupling.

The design of the trigger coupling is realized by separating the path . The low-frequency suppression path filters out low-frequency components through an RC high-pass filter. The signal of the DC coupling path is coupled to the rear stage through the AL1128 RF switch tube, and the AC coupling is coupled through the AL1128 through a 10uF capacitor. In the latter stage, the high-frequency suppression is passed through a switch RC filter. When the control terminal is given a high level, the high-frequency
transistor ALG430 is saturated and turned on, and the high-frequency signal components are filtered out through the RC low-pass filter.

ADC

The best input mode of ADC is differential input, the common mode voltage is 0.5V, and the dynamic range of input signal is 1.2Vpp.
ADC single-chip sampling rate can reach 2.5GSPS, resolution is 12bit, and has good linearity.

some knowledge points

At present, there are mainly two design methods for the frequency response of an oscilloscope: one is a Gaussian curve; the other is a flat curve.

It is difficult for the digital interface of FPGA to accept digital signals with a frequency above 600MHz, and this designtrigger frequencyUp to 1GHz, so it is necessary to design a frequency division circuit.

The low-noise variable gain amplifier circuit determines the gain and attenuation range of the signal conditioning channel, and is also the main source of noise in the signal conditioning channel. The monolithic PGA (Programmable Amplifier) ​​has limited bandwidth due to its gain range. This design is realized by cascading programmable attenuators and broadband fixed-gain amplifiers. In order to optimize the noise performance, usually the gain of the first-stage amplifier is as large as possible, and the noise figure is as small as possible.

External trigger signal, the trigger channel also needs impedance conversion circuit and attenuation circuit to complete the external trigger signal conditioning.

The noise was simulated by TINA-TI simulation software . TINA-TI of Texas Instruments (TI) can analyze the noise of the operational amplifier, and can graphically display the equivalent output voltage noise density of the amplifier, the effective value of the total output noise voltage, and the signal-to-noise ratio. It can be conveniently used to evaluate the noise performance of the amplifier.

The broadband impedance transformation circuit mainly completes the buffering of the input signal and reduces the load effect of the subsequent stage, which is a key circuit of the broadband oscilloscope. **The bandwidth of the voltage follower circuit or non-inverting amplifier circuit implemented by the op amp is limited, and it is difficult to reach the bandwidth of GHz. **And the input impedance of the op amp is limited, usually MΩ level, and the high-impedance input impedance of the oscilloscope is 1MΩ, which will inevitably produce a load effect, resulting in attenuation of the signal input to the post-stage amplifier . At the same time, the noise of the operational amplifier is relatively large. According to the analysis of the noise figure of the cascaded amplifier in the previous 3.1.3.2 summary, the smaller the noise figure of the front stage of the amplifier circuit, the better.

The simulation uses OrCAD PSpice to simulate the circuit, which has a relatively rich component library and circuit Spice model, and can easily perform four common simulations :
Time domain transient analysis (Time Domain): It is convenient to observe waveforms at different times, through Adding an excitation source can easily observe the waveform of each point, which is equivalent to the function of an oscilloscope.
DC sweep analysis (DC Sweep): It is possible to change a DC flow and observe its influence on the output.
AC sweep parameter analysis: observe the frequency response, amplitude-frequency characteristics, etc. of the circuit.
DC bias point analysis (Bias Point): It is convenient to observe the DC operating point of the circuit.

The function of bias voltage adjustment is : when a signal with a large DC bias and a small signal amplitude is input from the outside, the waveform can be adjusted from outside the screen to inside the screen by adjusting the bias voltage, so as to facilitate the observation of the waveform.

Usually the fixed attenuation factor of the passive attenuation network should be less than 100 times (40dB) (limited by the isolation of high-frequency relays and the influence of the attenuation factor of the passive attenuation circuit on the bandwidth).

Since the high-speed ADC usually works in a differential input mode (good for suppressing common-mode noise and anti-interference), it is necessary to convert the single-ended signal into a differential signal output. The conversion from single-ended to differential can be realized by differential operational amplifiers, RF baluns, and transformers.
The transformer is a coil passive device with low noise, but the transformer cannot pass DC.
RF baluns have high bandwidth and flat in-band, but they cannot provide gain and cannot pass DC signals.
The fully differential operational amplifier is an active device, which can complete gain design, single-ended-differential conversion, common-mode voltage adjustment, filtering and other designs, and has become a common choice for ADC driver design.

When designing a differential op amp, it is necessary to consider the input impedance design of the differential op amp, the allowable input common-mode voltage range, bandwidth and slew rate, coupling method, noise, harmonic distortion, stability, etc.