Logisim's construction of Moore type and Mealy type FSM
The difference between Moore type and Mealy type
According to the black book, the output of the Moore-type state machine depends only on the state of the system, while the output of the Mealy-type state machine depends on the state and input of the current system. Such an explanation may be difficult to understand. We can distinguish the Moore type from the Mealy type in this way:
Assume that there is an input in, a state S, and an output out.
- For the Moore type:
out is a combinatorial logic about S but not about in, that is, each S corresponds to an out (of course, the out of multiple Ss may be the same, that is, out = f(S)), as long as the current state When S changes, out changes accordingly. - For the Mealy type:
out is a combination logic about S and in, that is, out = f (S,in), which means that in a state S, if in changes, out will also change immediately.
Now that you know what Moore and Mealy are, let's try to build them~
Build a Moore-type circuit
As shown in the figure below, a register is used to store the current state, the transfer circuit obtains the next state through the current state and the input, and the output circuit obtains the output value out according to the current state. In fact, since both the transfer circuit and the output circuit are just a combinational logic circuit, we can simply use two modules to realize them respectively. (The digits of in and out in the figure are handled according to the actual situation, here are recorded as two digits) modules.
- transfer circuit
According to the state transition diagram we drew, adjust the table in the Combinational Analysis of logisim. You must pay attention to the high and low bits . If you use a splitter in logisim, you will find that the default high bit is below (as shown in the left picture), and When writing a table, in order to facilitate self-identification of the state, S1 will be written in front of S0 (as shown in the middle picture), and the circuit generated by such a key is high on the top (as shown in the right picture). At this time, directly connect the splitter to the There's going to be a big problem.
- output circuit
This circuit is very simple, we only need to continue to use the fool key of logisim to output out according to S, the same reason, pay attention to the high and low bits.
Building a Mealy-Type Circuit
Similar to the Moore type, only the output circuit is determined by the current state and the current input in from only the current state. Other precautions and the process of building the two modules are similar to the Moore type.
State Transition Diagram of Moore Type and Mealy Type
It is very simple to build a circuit, but it is still possible to make mistakes just by following the above method, because the most important part of the state machine problem should be how to draw the correct state transition diagram. Let's take a look at the difference between the two and what should be paid attention to when building.
- the difference between the two
The number of states of the Mealy type is 1 less than that of the Moore type , assuming that the Moore type has states (A, B, C, D, E), where when the input in is 1, the state D will transfer to the state E, and the Mealy type is only Four states are required: (A, B, C, D). This is because the output out of the Moore type is only related to the state. If the output out is 1 when the state is E, the E state must be formed. For the Mealy type, the output out is determined by the state and the input, that is, if the input in is 1 in the state D, then the output circuit can output 1, and there is no need to wait until the state E is formed, so the state E is not required , one less state than the Moore type.
- Precautions
The last state transition does not necessarily return to the initial state . When we perform string matching, when the last character is matched, then if the input is the first letter of the string or the input can form a string with the previous characters The prefix of , should transfer the state to the corresponding state instead of the initial state. For example, match 101 (when the last 3 digits of the input are 101, output 1), the input in sequence is 10101, assuming the state is as follows, then when the third digit is matched, the state is D, output 1, and the next input is 0 It will make the state directly skip the initial state and reach state C.
| state | meaning |
|---|---|
| A | not matched |
| B | matched to 1 |
| C | matched up to 10 |
| D | Matched to 101 |
- eg
Match 101 (output 1 when the last 3 digits of the input are 101): Carefully draw the state diagram as follows according to the above precautions. Among them, the output of the Moore type is only related to the state, so the output is marked under the state; the output of the Mealy type is related to the state and the input in, so it is marked in/out on the arc, which means that when it is at the starting point of the arc In the state, input the value that should be output by in and out. For example, if the arc from S2 to S1 is marked with 1/1, it means that when the state is S2, if in is 1, 1 will be output.
Realization of synchronous reset and asynchronous reset
When doing a question, you may encounter these two different reset requirements. If you require an asynchronous reset, it is relatively simple, because the reset that comes with the register in logisim is an asynchronous reset. Therefore, if the question requires an asynchronous reset, you only need to connect the reset signal to The Clear pin that comes with the register. And if synchronous reset is required, a two-to-one multiplexer can be used , as shown in the figure, when reset is 0, the selector will select the next state signal, if reset is 1, it will select 0, that is, reset. Since the register is only read on the rising edge of the clock, if reset is 1 at this time, 0 (reset) will be read in, which realizes a synchronous reset.
write at the end
This is the first time I write a blog. If I make a mistake, I hope you can correct me orz, and hope that P0 can pass.