Chapter 4 Data Transmission and Input/Output Interface

Chapter 4 Data Transmission and Input/Output Interface

The data transmission between the CPU and the peripherals does not have an address bus, but is carried out by the interface chip through the transfer and bridge.

There are three ways to communicate between CPU and data:

Queries, Interrupts, and Direct Memory Access (DMA).

• Inquiry: The CPU continuously inquires whether the I/O device is ready through the program, so as to control the exchange of information between the I/O device and the host. The disadvantage of this query method is that if the device status is not ready, the CPU will keep stepping and waiting, which will affect the execution efficiency of the CPU.

• Interruption: After the CPU starts the I/O device, it does not inquire whether the device is ready, but continues to execute its own program, and only responds when the device is ready and sends an interrupt request to the CPU. In this way, the phenomenon of "stepping" of the CPU can be avoided and the utilization rate of the CPU can be improved.

  Only after receiving the request from the I/O device, the data will be read from the interface to the CPU and then to the main memory (relying on the interrupt program service ISR implementation), and the cycle will be repeated until the data transmission is completed.

Interrupted process:

The device sends an interrupt request to the CPU, and the CPU detects the interrupt request in each bus cycle and grants the corresponding interrupt permission ( disable interrupt: prevent other interrupt signals to save the interrupt point program and go to the first address of the interrupt handler set by the device ) , then protect the site (terminal service program save environment, open interrupt process, retrieve environment)

last interrupt return

8086/8088 interrupt

• 8086 uses 8-bit binary code to represent an interrupt type, and there are 256 interrupts in total.
• Interrupts are divided into external interrupts and internal interrupts
• 8086 interrupt vector table: conversion table of interrupt type number and corresponding terminal service function entry address
  • Each interrupt type corresponds to an interrupt vector, which consists of four bytes
    • High address byte: the segment address of the code segment storing the interrupt service routine
    • Low address byte: store the offset address of the interrupt service routine
  • Address range:
  • 00000H - 03FFFH

Direct Memory Access :

DMA refers to the interface technology that the external device directly exchanges data with the system memory without going through the CPU. Usually the system bus is managed by the CPU. In the DMA mode, it is hoped that the CPU will let these buses out, that is, the lines connected to these buses by the CPU are in the third state (high-impedance state), and the DMA controller takes over and controls The number of bytes transferred, to determine whether the DMA is over, and to signal the end of the DMA.

Suitable for high-speed data transmission.

8253 Timers and Counters

control word register

Write the lower 8 bits first, then the upper 8 bits.

• six ways of working

  mode 0: count end interrupt

  

  • When the counter finishes writing the count value, it starts counting (software trigger), and the corresponding output signal OUT becomes low level. When the counter decreases to zero, OUT outputs high level immediately.
  • When the gate control signal is high level, the counter works; when it is low level, the counter stops working, and the count value remains unchanged
  • During the operation of the counter, if a new count value is rewritten, the counter will re-work according to the newly written count value, which can realize the function of repeated counting

  mode 1: Programmable monostable pulse

  

  • After writing the counting initial value, the counter starts to work. The rising edge of the gating signal GATE is valid before it starts to work (hardware trigger), so that the output OUT becomes low, and the output does not become high until the counter decreases to 0.
  • During the operation of the counter, when there is another rising edge on GATE, the counter reloads the original count initial value and starts counting again
  • If a new counting initial value is written to the counter during operation, it will not start working with the newly written counting initial value until the current counting value is full and returns to zero and the gate signal has a rising edge again.

  mode 2: frequency divider

  

  • Once the counting initial value is set, the counter can automatically repeat the subtraction "1" operation, and the subtraction "1" counts back to "0", and a negative pulse signal can be output at the output terminal
  • After writing the counting initial value, GATE is high and starts to work. When the counter is 0, OUT outputs a negative pulse with a clock pulse width and then automatically returns to high level; at the same time, it automatically reloads the original counting initial value and counts repeatedly
  • If a new counting initial value is written to the counter during work, it will not start working according to the newly written counting initial value until the current counting value is full and returns to zero.
  • During the operation of the counter, when GATE is low, it stops counting. After GATE recovers, the counter reloads the original counting initial value and restarts counting.

  mode 3: square wave output

  

  • The working mode of mode 3 is basically the same as that of mode 2, and it also has the function of automatically loading the time constant (counting initial value)
  • The difference is that when working in 3 mode, the output of pin OUT is not a negative pulse of one clock cycle, but a square wave with a duty ratio of 1:1 or approximately 1:1. When the count value is even, the output is high level during the first half of the counting process, and is low level during the second half of the counting process; when it is an odd number, the high level is one clock pulse wider than the low level

  mode 4: software trigger strobe

  

  • The output OUT starts to change to a high level, and when the GATE is high, it starts counting after writing the count value. When the counter decreases to zero, OUT outputs a negative pulse with a width of one clock pulse, then restores high level, and keeps high level all the time
  • When the gating signal GATE is high level, the counter works, and when it is low level, the counter stops working, and after returning to high level, the counter starts to subtract 1 from the original counting initial value.
  • During the operation of the counter, if the new counting initial value is rewritten, the current counting state will not be affected, and only after the current counting value is recorded, the counting value will work according to the written counting value

  mode 5: hardware trigger strobe

  

  • The counter is triggered by the rising edge of GATE to start working
  • When the initial counting value is written, the counter does not start counting immediately, but starts counting from the rising edge of the gate signal
  • During the counting process (or after the counting ends), if the gate signal has a rising edge again, the counter will start counting again from the original counting initial value.

8255A parallel chip

• The control register is generally placed at the last address.

Chip structure:

• Data bus buffer: D7-D0connected to the system data bus, responsible for data exchange with the CPU. Including input and output data, control word and status word
• Read and write control logic: read and write signals, chip select signals, A1A0select input pins for ports (ABC port)
• Group A control and group B control: Group A controls the upper 4 bits of port A and port C, group B controls the lower 4 bits of port B and port C
• Ports A, B, and C: their external leads are PA7～PA0, PB7～PB0and , respectively PC7～PC0. C port can be divided into two 4-bit ports: C port high 4 bits ( PC7～PC4) and C port low 4 bits ( PC3～PC0).

Three ways of working:

• Mode 0: basic input and output mode

  • Applies to unconditional transfer method
  • Latch capability for input, no output for output

• Mode 1: Strobe input and output mode

  • Suitable for program query and interrupt control mode
  • A port and B port are usually used for I/O data transmission, and C port is used as a connection line between A port and B port to transmit data in an interrupt mode
  • In mode 1, both A port and B port can strobe output data, and the 6 lines of C port are used as strobe control signals: PC3、PC6、PC7cooperate with A port, PC0、PC1、PC2cooperate with B port;

• Mode 2: Two-way transmission mode

  • Only port A can work in this way
  • Both the input and output of port A have data latch capability, and the input and output of data can cause interruption
  • Suitable for program query and interrupt control mode
  • At this time, port B can work in mode 0 or mode 1, and the remaining 3 lines of port C can be used as input and output lines or control lines in mode 1.

• Application: dynamic display and matrix keyboard

  

  PC7 - PC4Indicates a row, PC3-PC0indicates a column, and 11011101indicates that the second row and the second column are pressed.

Features of serial communication

• Serial communication refers to a communication method in which data is transmitted bit by bit
• Suitable for long-distance communication
• According to whether the clocks of the sending and receiving parties are unified, it can be divided into synchronous transmission and asynchronous transmission.

Transmission process of serial communication (asynchronous word frame)

In the asynchronous mode, the sending and receiving ends have independent bit timing clocks, and the data transmission rate is agreed by both parties. The sending and receiving parties use the data itself to synchronize. When the clock deviation of the two parties is not large, as long as the bit clock in a synchronization cycle does not exceed 1 transmission bit, the condition for correct reception can be met.

A frame of information is composed of four parts: start bit, data bit, parity check bit and stop bit.

• Start bit: It is a one-bit wide low level after the high level, and its falling edge represents the clock relationship, notifying the receiver that the transmission starts
• Data bits: 5 to 8 bits, specifically agreed by both parties through software
• Parity bit: check the parity of the data; it can also not be used
• Stop bit: It can be 1 bit, 1.5 bit or 2 bits, and the details are agreed upon by both parties. Active high, that is, the high level of the stop bit indicates the end of a character

Asynchronous serial communication typically identifies the following errors

• Parity error: The receiver calculates the parity according to whether the number of 1s is odd or even, and compares it with the expected value; it can be interrupted or queried when it is inconsistent; the work of the interface device is not prohibited
• Frame error: A binary sequence starting with a start bit and ending with a stop bit is a frame. If the receiver does not receive enough stop bits, it is a framing error. There are many reasons, such as problems with the receiver or transmitter, interference on the transmission line, or transmission clock error exceeding the allowable value. Just report an error without specifying the reason
• Overflow error: the microprocessor cannot remove the data in the shift register in time, and the latter data will overwrite the previous data

Interrupt or query; does not inhibit the operation of the interface device

• Frame error: A binary sequence starting with a start bit and ending with a stop bit is a frame. If the receiver does not receive enough stop bits, it is a framing error. There are many reasons, such as problems with the receiver or transmitter, interference on the transmission line, or transmission clock error exceeding the allowable value. Just report an error without specifying the reason
• Overflow error: the microprocessor cannot remove the data in the shift register in time, and the latter data will overwrite the previous data

RS-232 logic levels are reversed