Vivado and HLS functional testing in Linux environment

1. Introduction

For the completed installation and operation of Vivado under Linux , this article mainly introduces the operation process of Vivado and HLS under the Linux operating system through a case where the LED light flickers, and conducts a simple test of the installed software functions.
HLS synthesizes the compilation of C code into Verilog or VHDL code. This article briefly analyzes the code generated by HLS, and also solves the error "Failed to generate IP" that may occur during the compilation process.

2. Vivado_HLS generates IP core

1. Run Vivado_HLS:
   The running process of Vivado_HLS has been introduced in the installation and operation of Vivado under Linux . Run the following command shell script to open HLS:

	source /opt/Xilinx/Vivado/2017.4/settings64.sh  ##Vivado在Linux下的安装路径
	vivado_hls

Open the interface as shown in the figure below:

2. Create a new project Create New Project, and create the project in the workplace folder under Documents for easy search:

3. The top-level module is named Top Function:

4. Select the FPGA model Part Selection and keep consistent with the selected model:

5. Create a new .cpp file, the code content is very simple, that is, the LED light flashes once every 50M clock cycles, and the IP core is compiled and generated:

The IP core is shown in the figure:

3. Vivado project calls IP core

1. Run Vivado:
   The running process of Vivado has been introduced in the installation and operation of Vivado under Linux . Run the following command shell script to open Vivado:

	source /opt/Xilinx/Vivado/2017.4/settings64.sh  ##Vivado在Linux下的安装路径
	vivado

2. After creating a new project, add the path where the HLS project is located in the IP Catalog, and you can see that the IP core generated by HLS has been successfully imported:

3. Create a new bd (Block Design) project, import the IP core, ap_rst is always low, and the ap_clk and led_V interfaces are externally connected:

4. ap_clk and led_V are bound to the crystal oscillator clock output and LED interface respectively:

5. After the synthesis is successful, a bit stream file is generated:

6. Since the clock is 50MHz, you can see that the LED flashes once per second after program device:

Four. HLS generates Verilog code analysis

Open the IP core generated by HLS and you can see the compiled Verilog code as shown below:

The naming is complicated and confusing, but based on the working principle of LED lights, it can be simply analyzed from the input and output interfaces:

The counter i_reg_39 is basically equivalent to i_1_fu_56_p2, assigning values ​​to each other to complete the counter function that depends on the input clock, and completing the flipping of the led_V output interface by comparing with 25M, and realizing the function of blinking every 50M clock cycles;

5. Problems and solutions during HLS operation

problem appear:

During the process of compiling the comprehensive project and generating the IP core in HLS, a "Failed to generate IP" error may appear, as shown in the following figure:

Solution:

This problem is usually caused by an earlier HLS version. For example, this project uses the 2017.4 version of HLS, so the system time needs to be changed to before 2018 to successfully generate the IP core: