1. What is make
make is a command tool, a command tool that interprets the instructions in a makefile.
2. Why learn the make command
Example: The compiler gcc we usually use on linux has 5 .c files ( a .c b .c c .c d .c e .c )
Compilation instructions: gcc a .c b .c c .c d .c e .c -o test
When we enter work, we need to compile many .c files, such as compiling hundreds or thousands of files. If we use the above method, it is not good.
The reasons are as follows:
1. It is easy to miss a certain .c file, resulting in compilation failure and time-consuming troubleshooting
2. When we have not missed any knocks and successfully generated executable files. But we need to modify a certain file and have to recompile every .c
3. When working, many of the codes we write need to be used across platforms. For example, when writing into ARM, we need to use the arm-linux-gcc command
Summary: Compilation is troublesome - in order to facilitate compilation, we need to learn make instructions and usage
3. Make solves the above problems very well
(1) Maintenance of a large number of code relationships
There are many source codes in the big project, manual maintenance, long compilation time and complicated compilation commands, making it difficult to remember and maintain. Therefore,
write the code maintenance command and compilation command in the makefile file, and then use the make tool to parse the file and automatically execute the corresponding command, which can realize the reasonable compilation of the code.
(2) Reduce repeated compilation time
When changing one of the files, you can judge which files have been modified, you can only re-edit the file, and then re-link all the target files to save compilation time
4. What is Makefile
Makefile is a file that describes the compilation rules of our program - similar to a script
When we execute the make command, the make command will find the Makefile file in the current directory, and compile the program according to the execution rules in the file.
Note: Makefile rule files are compilation rules written by our programmers according to their own programs.
Five, the benefits of using Makefile
1. Simplify the input command when compiling the program, such as the above gcc a .c b .c c .c d .c e .c -o test
Directly enter a make to complete the compilation
2. Save compilation time and improve compilation efficiency
6. Grammatical rules of Makefile
Object files: list of dependent files
<tab> Compile command // <tab> This is the tab key
clear：
<tab> rm target file -rf //Use the make clear command: delete the generated target files
1. Target file:
Usually we finally compile the executable file
2. Dependency files
is the file used to input the resulting object file
An object file usually has several dependent files (or only one)
gcc dependent file dependent file -o object file (multiple dependent files)
gcc dependency file -o object file (a dependency file)
In addition: the dependent file of the target file can be a .c file or a .o file
For example: There are three .c files and one header file, which are: main .c a .c b .c head.h
(1) The usual compilation mode
(2) Use the make command to complete the compilation
Step 1: In the current location, create a Makefile
Directive: vim Makefile
Step 2: Specify compilation rules according to the compiler .c file
The first type of writing (not commonly used and cannot see which file has been modified, cross-platform cannot be used - compilation will fail)
Enter the make command and execute the file
Output result and delete operation demo
The second type of writing (you can check which file has been modified, but it cannot be used across platforms-compilation will fail)
Enter the make command and execute the file
Output result and delete operation demo
The third type of writing (you can view file modification, and can also be used across platforms) is based on the second type of writing and adaptation - don't understand Section 8
Seven, make command format
All the previous uses are separate make , don't they all use separate make? Answer: no
Simply speaking, using make alone is related to the name of the created Makefile.
By default , make looks for files named: GNUmakefile , Makefile , and makefile in the working directory as makefile input files.
Simply speaking, it is to create one of the names: GNUmakefile, Makefile, makefile ,
You can use a single make command
If you are not creating one of the above 3 types, you must use make -f file name
For example: create a Makefile1 (this Makefile1 is not the above three)
You can't use a separate make command but use make -f Makefile1
8. Custom variables of Makefile (after learning this section, you have basically mastered it)
Define variables:
variable name = variable value
Quote variable:
$(variable name) or ${variable name}
Makefile variable name: can start with a number.
8.1 Example: as shown in the figure below (this example is the first way of writing)
become as shown below
Analysis: $(cc) is gcc, but this $(cc) can be compiled across platforms
$(obj) is main.c ac bc
Similarly: $(target) is main
In short, just change the name, with the same meaning as the original picture.
Why do you want to do this, convenient, fast,
When we have thousands of .c files, we can directly replace thousands of .c files with a name and refer to it $(name)
8.2 Example: as shown below (this example is the second way of writing)
Suddenly found that when we have hundreds of .c files, there are a lot of codes written in this way. Therefore, see Section 9, how to write simpler codes.
9. Predefined variables
There are many predefined variables in the makefile, which have special meanings and can be used directly in the makefile.
Commonly used are:
$@ target name (that is, the left side of " : " is the target name) such as main: main.c (main is the target name)
$< The first file in the dependent file list such as; main: main.c ac bc ($< is the first main.c in red font)
$ ^ All dependent files such as; main: main.c ac bc ($^ is the red font)
CC The name of the C compiler, default is cc
CFLAGS options for the C compiler
The perfect rules are as shown in the figure below
Learn, double-click to like it!!!