RTL8211 Instructions for use

1 Overview

Realtek's RTL8211F-CG/RTL8211FD-CG/RTL8211FI-CG/RTL8211FDI-CG are highly integrated Ethernet transceivers that comply with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3 standards. It provides all the necessary physical layer functions to send and receive Ethernet packets over CAT.5 UTP cables. The RTL8211FI and RTL8211FDI are industrial grade.

RTL8211F(I)/RTL8211FD(I) uses advanced DSP and analog front-end (AFE) technology to realize high-speed data transmission through UTP cable. Functions such as crossover detection and automatic correction, polarity correction, adaptive equalization, crosstalk cancellation, echo cancellation, timing recovery and error correction are implemented in RTL8211F(I)/RTL8211FD(I) to provide 10Mbps, 100Mbps or 1000Mbps time robust transmit and receive capabilities.

1000Base-T, 10Base-T and 100Base-TX data transmission between MAC and PHY is realized through RGMII interface. The RTL8211F(I)/RTL8211FD(I) supports multiple RGMII signal voltages, including 3.3, 2.5, 1.8 and 1.5V.

2 RTL8211F-CG features :

• Compatible with 1000Base-T IEEE 802.3ab standard
• Compatible with 100BASE-TX IEEE802.3u standard
• Compatible with 10Base-T IEEE 802.3 standard
• Support RGMII
• Supports IEEE 802.3az-2010 (Energy Efficient Ethernet)
• Built-in wake-on-lan
• Support interrupt function
• Support parallel detection, cross detection and automatic correction, automatic polarity correction
• Support PHYRSTB core power off
• Baseline Drift Correction
• Support 120mCAT.5 cable transmission based on 1000Base-T
• Built-in switching regulator and LDO, optional 3.3/2.5/1.8/1.5 signal RGNII
• Support 25MHZ external crystal oscillator
• Provide 125MHZ MAC clock source
• Provides 3 network status LEDs
• Support link energy saving function
• green ethernet
• QFN40 green package
• 55 nm process, ultra-low power consumption
• Industrial-grade manufacturing process (RTL8211FI/RTL8211FDI)

3 System application

• Digital Television
• MAU (Media Access Unit)
• CNR (Communications and Networks Hoist)
• game console
• Printers and Office Machines
• DVD player and VCR
• ethernet hub
• ethernet switch

Additionally, the RTL8211F(I)/RTL8211FD(I) can be used in any embedded system that requires an Ethernet MAC over a UTP physical connection.

3.1 RTL8211F(I) application block diagram

 

3.2 RTL8211FD(I) application block diagram

 

4 System Block Diagram

 

5 pin diagram

 

6 Pin description

Interace	Pin No.	Pin name	Type	Description
Transceiver Interface	1	MDIP0	IO	the BI_DA+/- pair
	2	MDIN0	IO
	4	MDIP1	IO	the BI_DB+/- pair,
	5	MDIN1	IO
	6	MDIP2	IO	the BI_DC+/- pair.
	7	MDIN2	IO
	9	MDIP3	IO	the BI_DD+/- pair.
	10	MDIN3	IO
CLOCK	36	XTAL_IN	I	25MHz Crystal Input.
	37	XTAL_OUT/EXT_CLK	O	25MHz Crystal Output.
	35	CLK OUT	O	125/25MHz Reference Clock
RGMII	20	TXC	I	transmit reference clock
	18	TXD0	I	Transmit Data. Data is transmitted from MAC to PHY via TXD[3:0].
	17	TXD1	I
	16	TXD2	I
	15	TXD3	I
	19	TXTL	I	Transmit Control Signal from the MAC
	27	RXC/PHYAD1	O	The continuous receive reference clock
	25	RXD0/RXDLY	O	Receive Data. Data is transmitted from PHY to MAC via RXD[3:0].
	24	RXD1/TXDLY	O
	23	RXD2/PLLOFF	O
	22	RXD3/PHYAD0	O
	26	RXCTL/PHYAD2	O	Receive Control Signal to the MAC
Management Interface	13	MDC	I	Management Data Clock
	14	MEDIUM	IO/PU	Input/Output of Management Data
	31	INTB/PMEB	About/From	Interrupt / Power Management Event
Reset	12	PHYRSTB	I	Hardware Reset. Active low.
LED	32	LED0/CFG_EXT	O	High=Link Up at 10/100/1000Mbps Blinking=Transmitting or Receiving
	33	LED1/CFG_LDO0	O
	34	LED2/CFG_LDO1	O
Regulator and Reference	39	RSET	O	Reference (External Resistor Reference).
	30	REG_OUT/LDO_OUT	O	For RTL8211F(I): Switching Regulator 1.0V Output. Connect to a 2.2µH or 4.7µH inductor.
Power and Ground	29	DVDD33	P	Digital non-RGMII I/O Power. 3.3V
	28	DVDD_RG	P	Digital RGMII I/O Pad Power
	21	DVDD10	P	Digital Core Power. 1.0V
	11,40	AVDD33	P	Analog Power. 3.3V.
	3,8,38	AVDD10	P	Analog Power. 1.0V.
	41	GND	G	Ground.

7 Hardware Configuration Instructions

Pin number	Pin name	pin type	application note
35	CLK OUT	O	125M clock source, if not used, must be left floating
14	MEDIUM	IO/PU	Need to add 1.5K pull-up resistor
22	PHYAD0	OR/LI/PD	PHY[2:0] Physical address setting
27	PHYAD1	OR/LI/PD
26	PHYAD2	OR/LI/PD
24	TXDLY	OR/LI/PD	Add pull, add 2ns TX clock delay
25	RXDLY	OR/LI/PD	加上拉，增加2ns RX时钟延时
32	CFG_EXT	O/LI/PD	上拉：IO PAD选择外部电源 下拉：IO PAD选择内部LDO电源