FinFET process flow chart

1. Introduction to FinFETs

FinFET is called Fin Field Effect Transistor (FinField-Effect Transistor; FinFET) is a new complementary metal oxide semiconductor (CMOS) transistor. Gate length can be less than 25 nm. The inventor of this technology is Professor Hu Zhengming of the University of California, Berkeley. Fin means fish fin, and FinFET is named according to the similarity between the shape of the transistor and the fish fin.

1.1 Main features

The channel region is a fin-shaped semiconductor surrounded by a gate. The length of the fin along the source-drain direction is the channel length. The gate-wrapped structure enhances the control ability of the gate and provides better electrical control over the channel, thereby reducing leakage current and suppressing short-channel effects.

1.2 Classification

Professor Hu Zhengming and others respectively designed bulk silicon FinFET devices (Fin FieldEfect Transistor, FinFET) and SOI FinFET devices.

On the basis of bulk silicon FinFET devices and SOI FinFET devices, a variety of structures with higher performance and lower power consumption have been derived, such as ring gate FinFET devices, Π-gate FinFET devices and Ω-gate FinFET devices. Based on SOI substrates, FinFETs with different structures have been realized, such as double-gate, triple-gate, Pi-gate, Omega-gate, ring-gate, etc.

2. FinFET process flow

The FinFET front-end process adopts a three-dimensional structure. The difficulty of the FinFET process is to form the shape of Fin. The following is a brief introduction to the different process flows of Fin.

2.1 Manufacturing steps and process details of Fin structure

2.1.1 Flowchart of making Fin by SADP process method

Step 1: Deposit an auxiliary layer on the clean silicon surface ① to form 〖Si〗_3 N_4 to obtain ②.
Step 2: Etch the auxiliary layer by photolithography to form a gate-like structure to obtain ③, the width of which is the spacing between adjacent Fins.
The third step: Deposit a layer of silicon oxide SiO_2 on the surface as a hard mask to obtain ④.
Step 4: By controlling the thickness of SiO_2, the width of Fin can be controlled to obtain ⑤.
Step 5: Use dry etching to form a shape similar to the gate sidewall, as shown in ⑥.
Step 6: Then remove the ⑥ auxiliary layer, and the remaining shape is the hard mask plate ⑦ that forms the ultra-thin Fin.
Step 7: ⑦Remove the hard mask after dry etching to form an ultra-thin Fin as shown in ⑧.

2.1.2 Flowchart of making Fin by sidewall transfer lithography technology

Step 1: grow and deposit a 4-layer stacked layer structure on a silicon substrate.
The second step: photolithography mask, SiN etching, polysilicon deposition to form side walls, and then dry etching.
Step 3: Remove SiN with phosphoric acid, leaving polysilicon sidewalls.
The fourth step: dry etching SiO_2, SiN and SiO_2 film layers.
Step five: use the ONO structure as a hard mask to dry etch to form a FIN structure.
Step 6: Fill the grooves between the FIN structures with an oxide layer, and then densify the oxide layer.
Step Seven: Chemical Mechanical Polishing (CMP).
Step 8: Wet etch back (etch-back) to form an oxide isolation region to expose the FIN structure.

2.2 Manufacturing steps and process details of the FinFET structure

Professor Hu Zhengming and others designed bulk silicon FinFET devices and SOI FinFET devices respectively, and developed different FinFET structures on this basis.
There may be some differences in the FinFET process flow of different structures. The following briefly introduces the process flow of the FinFET structure.

2.2.1 Process steps of gate full surround FinFET based on bulk silicon substrate

The first step: By adjusting the deposition conditions, the PECVD method can achieve a step coverage of about 50% to obtain (b).
Step 2: Etch back SiO_2 isotropically, control the time of etching back, remove SiO_2 on the sidewall of Fin, and keep SiO_2 on the upper surface of the substrate and the upper surface of Fin, as shown in figure (c).
Step 3: Using a similar method, deposit non-conformal 〖Si〗_3 N_4. After isotropic etching back, the 〖Si〗_3 N_4 on the sidewall of the Fin is removed, while the upper surface of the substrate and the upper surface of the Fin 〖Si〗_3 N_4 is retained to obtain (d).
The fourth step: deposition and anisotropic etching back to form SiO_2 sidewalls to protect the sidewalls of Fin, the result is shown in Figure (e).
Step 5: Define the channel position by photolithography, the source and drain parts〖Si〗_3 N_4 are protected by photoresist, and the 〖Si〗_3 N_4 not protected by photoresist is removed by selective etching. In this way, the silicon surface below the channel region is exposed, as shown in Figure (f).
Step 6: Further adopting an isotropic etching process, the exposed silicon is etched, and finally a structure suspended below the channel region is formed, as shown in figure (g).
Step 7: After etching away SiO_2 and 〖Si〗_3 N_4, SiO_2 is re-deposited, and through planarization and etching back processes, only a layer of SiO_2 is left on the bulk silicon substrate for the gap between the gate and the substrate isolation.
Step 8: By controlling the thickness of the SiO_2 layer, ensure that there is a gap between the suspended Fin and SiO_2, the result is shown in Figure (i).

Note: Subsequent processes, such as channel implantation, gate dielectric layer formation, polycrystalline gate definition, sidewall formation, source-drain implantation, and silicide contact, are all the same as conventional FinFET processes.

2.2.2 Silicon germanium channel PMOS FINFET structure process

The block diagram and flow chart of the fabrication process of the silicon-germanium channel PMOS FINFET are respectively shown below.

Block diagram of the fabrication process of silicon germanium channel PMOS FINFET

Fabrication flow chart of silicon germanium channel PMOS FINFET

Step 1: Preparation of epitaxial silicon wafers with micron-scale thickness.
The second step: deposit oxide and nitride as a hard mask (Hard mask).
Step 3: Photoetching the hard mask and silicon substrate (right-angle etching), depositing a thick oxide layer to the specified coordinates as the STI area, and etching the oxide layer to leak out the silicon FIN.
Step 4: Deposit a thin oxide cap layer as a protective layer for subsequent implantation.
Step 5: well implantation and threshold voltage adjustment implantation.
Step 6: Rapid thermal annealing (RTA) in the well region.
Step Seven: Remove the remaining sacrificial oxide layer with diluted hydrofluoric acid (HF).
Step 8: Selectively epitaxially grow a silicon germanium channel structure (including the bottom silicon buffer layer, the middle silicon germanium layer, and the upper silicon cap layer) on the bare silicon FIN structure.
Step 9: Growth of the gate oxide layer.
Step 10: Deposit and form an undoped polysilicon gate, and form a gate by exposing and etching the polysilicon.
Step 11: Deposit oxide and nitride as compensation sidewalls. Depositing oxide is to oxidize the polysilicon twice to eliminate the stress on the surface of the polysilicon.
Step 12: Halo (HALO) implantation: B ions are implanted at a certain angle to form a HALO structure.
Step 13: S/D Extension implantation: Low-energy ion implantation forms a source-drain extension (SDE) structure.
Step 14: Deposit and grow nitride as the second side wall.
Step 15: Source and drain (S/D) implantation.
Step 16: Rapid laser annealing after implantation.
Step 17: Deposit NiSi alloy as contact silicide (Contact silicidation).
Step 18: Form source, gate, drain and silicon substrate contacts, make contact holes (Contact) and Metal.
The nineteenth step: back metal layer and via (Metal and Via) and passivation layer process.

2.2.3 SOI FinFET process flow chart

The first step: (a) first cover the substrate with a hard mask layer on the upper surface of the bulk silicon.
Second step: (b) Obtain silicon fins.
Step Three: (c) Oxide Deposition.
Step Four: (d) Gate Oxide Deposition.
Step 5: (e) Bulk FinFET device after polysilicon deposition.
Step 6: (f) FinFET finally gets the device.

2.2.4 Main process steps of Fin FET

The first step: (a) First oxidize a layer of SiO2 film on the bulk silicon to release the excess stress during the process, and then deposit the SiN layer.
The second step: (b) Use a specially designed silicon island mask to perform deep ultraviolet exposure, and obtain silicon fins after several times of etching.
The third step: (c) SiO2 sacrificial layer is formed by oxidation on both sides of the silicon fin.
Step 4: (d) Etch to remove and completely peel off the SiO2 sacrificial layer to remove the damage caused by etching.
The fifth step: (e) grow a very thin gate oxide layer on both sides of the silicon fin.
Step 6: (f) Deposit polysilicon, and form a polysilicon gate after exposure, etching and other processes.

Note: The subsequent process steps are similar to the planar silicon MOS process.

3 Summarize the FinFET process

The main process of FinFET process includes fin etching, oxide deposition, oxide chemical mechanical polishing, oxide etching, gate oxide layer deposition, polysilicon deposition and other steps.