SystemVerilog syntax (2) use of struct, enum, union

Table of contents

struct

enum

union


struct

Struct is a user-defined data type, which can contain multiple member variables of different types, similar to the structure in C language. Struct can be used to describe complex data structures to facilitate data organization and access.

The syntax for defining a struct is as follows:

struct struct_name {
    data_type member1;
    data_type member2;
    ...
};

struct_name: the name of the structure

member1, member2: member variables of the structure

data_type: The data type of the member variable.

For example, here is a struct with three member variables:

struct person {
    string name;
    int age;
    float height;
};

A variable of type struct can be declared using the following syntax:

person   p1;

Member variables can also be initialized at declaration time:

person p2 = {"Tom", 20, 1.75};

To access the member variables of struct, you can use the "." operator:

p1.name = "Jack";
p1.age = 25;
p1.height = 1.8;

struct can also be defined nested, for example:

struct address {
    string street;
    string city;
    string state;
};

Nest address in person, as follows:

struct person {
    string name;
    int age;
    address addr;
};

In this way, the addr member variable in the person structure is a nested address structure.

To access the member variables of addr, you can use the "." operator:

person p3 = {"Lucy", 30, {"Main St.", "New York", "NY"}};
p3.addr.street = "Broadway";
p3.addr.city = "Los Angeles";
p3.addr.state = "CA";

enum

An enum is a data type used to define a limited set of named constants. It can be used to represent the state of the state machine, the bit field of the register, the error code, etc.

Here is an example of a simple enum definition:

enum logic [3:0] {
    IDLE,
    READ, 
    WRITE, 
    ERROR
} state;

This enum defines a variable called state, which has 4 possible values: IDLE, READ, WRITE, and ERROR. Each value is represented by a 4-bit binary number ranging from 0 to 15.

The enum type can also be defined as a new data type using the keyword typedef, for example:

typedef enum logic [1:0] {
    RED, 
    YELLOW, 
    GREEN
} traffic_light_t;

This definition defines traffic_light_t as a new data type that can only take on three values: RED, YELLOW, and GREEN.

When calling, use traffic_light_t as the defined data type, as follows, define the current state and next state, and its state can only be the three listed in enum.

traffic_light_t  state; 
traffic_light_t  next_state;

union

A union is a data type that allows different types of data to be stored in the same memory location. It is similar to a union in C, but in SystemVerilog, it can contain any type of data, including structures and arrays.

Here is a simple union example:

typedef union packed {
  logic [7:0] byte;
  struct packed {
    logic [3:0] nibble1;
    logic [3:0] nibble2;
  } nibbles;
} my_union;

In this example, we define a union named my_union. It has two members: byte and nibbles. byte is an 8-bit logical type, and nibbles is a structure containing two 4-bit logical types.

We can access the members of the union using:

my_union u;
u.byte = 8'hAB;
u.nibbles.nibble1 = 4'hA;
u.nibbles.nibble2 = 4'hB;

In this example, we first create a variable named u of type my_union. Then, we assign 8'hAB to the byte member, and 4'hA and 4'hB to the two members of the nibbles structure respectively.

It should be noted that when we access the members of the union, we can only access the last assigned member.

For example, if we first assign 8'hAB to byte, and then assign 4'hA and 4'hB to two members of the nibbles structure, then we can only access the nibbles member, not the byte member.

In summary, a union is a very useful data type that allows storing different types of data in the same memory location. It can be used to implement features such as polymorphism and bit fields.

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Origin blog.csdn.net/m0_61298445/article/details/129876314