Slvi driver debugging summary
This article is a summary of some problems encountered in the debugging process of 4G projects after the introduction of basic audio knowledge.
Curiosity is the driving force for progress.
Slvi
driver debugging summary 1
1 Simulation of spi communication problems 3
2 msleep and mdelay 3
2- 1 System resource 3
2-2 Time control precision 3
3 I2C communication problem 4
3.1 I2C bit transfer 4
3.2 Start and end signal 4
3.3 I2C response signal 4
3.4 I2C write register 4
3.5 I2C read register 5
4 Timer usage 8
5 Interrupt up and down Two problems 9
6 nau8810 chip pcm data, si_3217x chip precautions 10
1 analog spi communication problem
Spi is the abbreviation of Serial Peripheral interface, that is, serial peripheral device interface.
The communication interface includes,
MISO: master device data input, slave device data output. Master input, Slave Output
MOSI: Master device data output, slave device data input. Master Output, Slave Input
SCLK: clock signal, generated by the master device
CS: slave device chip select signal, controlled by the master device. When the chip select of the slave device is pulled low, the data information can be obtained from the SPI bus.
According to whether the SPI is configured as a master or a slave mode, the functions of the MIMO and MOSI pins will automatically change to realize the switching between sending and receiving.
Problems encountered :
Use the analog spi to read and write registers, the data is abnormal. The data written is incorrect.
Troubleshooting:
It takes a delay after simulating spi to read and write reg, otherwise the read and write data will be abnormal.
2 msleep and mdelay
both have the function of delay, but there is a big difference:
2-1 system resource
mdelay occupies cpu resources, other functions cannot use cpu at this time
msleep does not occupy cpu resources, other functional modules can use cpu
2- 2. Time control accuracy
Mdelay time control is accurate and can reach the ms level. For example, mdelay (2), the actual wait is also 2ms
. Msleep time control scale is 10ms. For example, msleep (2), the actual sleep is more than 10ms. Because the calling thread will sleep, after sleeping for 10ms, depending on the thread priority, it may still not be executed immediately, so it is generally greater than 10ms.
Problems encountered:
Using mdelay and msleep respectively in Spi delay, the effect is completely different. Using msleep to load the driver's patch is very slow. After replacing mdelay, the speed is faster, but it will consume more cpu resources.
3 I2C communication problems
I2C protocol, 2 bidirectional serial lines, a data line SDA, a clock line SCL.
3.1 I2C bit transfer
3.2 Start and end signals
Start signal: SCL is high, SDA transitions from high to low, and data transmission starts
3.3 I2C response signal
3.4 I2C write register
1. Master initiates START
2. Master sends I2C addr (7bit) and w operation 0 (1bit), waits for ACK
3. Slave sends ACK
4. Master sends reg addr (8bit), waits for ACK
5. Slave sends ACK
6. Master sends data (8bit), that is, the data to be written in the register, and waits for ACK
7. Slave sends ACK
8. Steps 6 and 7 can be repeated multiple times, that is, write multiple registers sequentially
3.5 I2C read register
1. Master sends I2C addr (7bit) and w operation 1 (1bit), waits for ACK
2. Slave sends ACK
3. Master sends reg addr (8bit), waits for ACK
4. Slave sends ACK
5. Master initiates START
6. Master sends I2C addr (7bit) and r operation 1 (1bit), waiting for ACK
7. Slave sends ACK
8. Slave sends data (8bit), which is the value in the register
9. Master sends ACK
10. Steps 8 and 8 9 steps can be repeated many times, that is, read multiple registers sequentially
the master device writes the NAU8810 codec through I2C, it finds that the written value is different from the read value. Write 0x15D to the register, the oscilloscope capture is as follows, as shown in Figure 3-5-1:
The read value register is as follows:
Read general diagram is shown in Figure 3-5-2
Read exploded diagram 3-5-3
The read value is 0x101 , Later, it was found that the I2C write data was not processed according to the chip's protocol. The above is a general protocol, but different chip manufacturers may be different. For example, nau8810 chip:
Nau8810 I2C write reg protocol is as follows:
Note: The data here is 9 bits and the register has only 7 bits. The highest bit of the data is placed in the control Register Address for transmission. Found this and solved the problem.
4 Timer use There is a problem during
debugging : the upper layer sets the handshake tone to generate ACK, and the waveform requirements are as follows:
first generate a 1400Hz tone for 100ms, then stop for 100ms, and then generate a 2300Hz tone for 100ms. The difficulty of the problem is that the time interval between the tone tone at 1400Hz and the tone tone at 2300Hz is required to be 100ms, and the deviation is 3% up and down. If the upper layer does this task, the control accuracy will not meet the requirements. Therefore, timer processing is used at the bottom layer, using methods:
1. Register timing A
init_timer();
2. Register task queue B
INIT_WORK();
3. Add timer
Add_timer();
When the timer expires, the function registered with the timer in the soft interrupt will be executed, and the functions in the task queue will be scheduled in this function, and the task queue will complete different required functions.
5 Interrupt upper
and We want the interrupt service routine to execute as quickly as possible, and at the same time want the program to complete as much work as possible, these two goals are obviously contradictory. Based on this contradiction, we divide the interrupt service routine. There are two parts: the top half and the bottom half.
1. The upper part: the execution starts immediately after receiving an interrupt, with strict time limit requirements, such as responding to the hardware device and resetting the hardware, which are all completed when all interrupts are disabled. The interrupt service routine is the top half.
2. The second half: There is no particularly strict time limit, allowing the work to be completed later to be divided into the lower half. Generally speaking, the second half will be executed immediately when the interrupt service routine returns.
The whole process of the interrupt activity is roughly: copy from: http://cache.baiducontent.com/c? ... 2b000179ca&p1=1
1. Interrupt request: Once the interrupt event occurs or the interrupt condition is formed, the interrupt source submits the "application report" ”, and requesting the CPU to temporarily put down the current work and turn it into an interrupt source as a special service
2. Interrupt masking: Although the interrupt source has submitted an “application report”, whether it gets a response from the CPU depends on whether the “application report” It can be sent to the CPU through 2 or 3 "levels" (interrupt masks) (the corresponding interrupt mask bit is equal to 1, which means the level is released; otherwise, the corresponding interrupt mask bit is equal to 0, which means the level is forbidden to pass);
3. Interrupt response: If it is released all the way, after the CPU responds to the interrupt, it records the interrupted work breakpoint (protects the breakpoint address to the stack), and suspends the "no longer accepting other application report cards" (clears the global interrupt flag bit GIE=0 ), jump to the interrupt service routine
4. Protect the site: the original work site may be damaged when dealing with new tasks, so it is necessary to properly protect the work site and working environment;
5. Investigate the interruption source: check which interruption source the "application report" Make targeted services;
6. Interrupt processing: Start targeted interrupt services for the identified interrupt sources;
7. Clear flags: After processing the corresponding tasks, it is necessary to cancel the registration (clear the interrupt flag), In order to avoid repeated responses;
8. Restoring the site: restore the previously protected work site, so as to continue the interrupted work;
9. Interrupt return: retrieve the interrupted work breakpoint (restore from the stack) Breakpoint address), and remove the "no more application report card" (GIE=1), continue to execute the work that was interrupted. In the
interrupt service subroutine:
A. The interrupt program cannot send or receive data to the user space
B , Can not do any operations that may cause dormancy, wait_event, or lock the semaphore
C, can not call the schdule function.
The spi device cannot be read or written in the interrupt, and can be placed in the lower half of the interrupt to do the spi read and write operations.
1. The upper part is required to be as fast as possible to increase the throughput of the system.
2. The lower half generally has processing methods such as soft interrupts, tasklets, and work queues.
6 nau8810 chip pcm data, matters needing attention in si_3217x chip
Problem nau8810 has noise:
problem analysis: the reason for the noise is that there are two data lines in the 4-wire pcm, one dataIn and one dataOut, because the audio module of the central control is not loaded , the hisi master is not configured with an internal codec, and dirty data is directly output to the codec, resulting in noise problems.
Solution: Power off the pcm data input/output module of nau8810 directly.
Problems in si3217x:
1. The problem of generating 2300Hz tone tone.
It is wrong to generate 2300Hz tone according to the software provided by the chip manufacturer, and there is a problem in the software calculation. Subsequently, according to the formula provided in the manual, manually calculate the value that should be configured to the register. The specific algorithm code is described and will not be repeated here.
2. Configure the ram register Configure the ram register in
strict accordance with the method provided in the chip manual. There is a detailed description in the code and will not be repeated here. The other is the configuration of the reg register No. 74. The value given by the technical support is not correct and needs to be modified to the value in the code.
3. Questions of doubts
Regarding the usage of the interrupt registers 17, 18, and 20 reg registers, the existing code is directly inherited from the mtk platform. I have consulted the technical support, but did not explain it clearly. I can understand it later.
This article is a summary of some problems encountered in the debugging process of 4G projects after the introduction of basic audio knowledge.
Curiosity is the driving force for progress.
Slvi
driver debugging summary 1
1 Simulation of spi communication problems 3
2 msleep and mdelay 3
2- 1 System resource 3
2-2 Time control precision 3
3 I2C communication problem 4
3.1 I2C bit transfer 4
3.2 Start and end signal 4
3.3 I2C response signal 4
3.4 I2C write register 4
3.5 I2C read register 5
4 Timer usage 8
5 Interrupt up and down Two problems 9
6 nau8810 chip pcm data, si_3217x chip precautions 10
1 analog spi communication problem
Spi is the abbreviation of Serial Peripheral interface, that is, serial peripheral device interface.
The communication interface includes,
MISO: master device data input, slave device data output. Master input, Slave Output
MOSI: Master device data output, slave device data input. Master Output, Slave Input
SCLK: clock signal, generated by the master device
CS: slave device chip select signal, controlled by the master device. When the chip select of the slave device is pulled low, the data information can be obtained from the SPI bus.
According to whether the SPI is configured as a master or a slave mode, the functions of the MIMO and MOSI pins will automatically change to realize the switching between sending and receiving.
Problems encountered :
Use the analog spi to read and write registers, the data is abnormal. The data written is incorrect.
Troubleshooting:
It takes a delay after simulating spi to read and write reg, otherwise the read and write data will be abnormal.
2 msleep and mdelay
both have the function of delay, but there is a big difference:
2-1 system resource
mdelay occupies cpu resources, other functions cannot use cpu at this time
msleep does not occupy cpu resources, other functional modules can use cpu
2- 2. Time control accuracy
Mdelay time control is accurate and can reach the ms level. For example, mdelay (2), the actual wait is also 2ms
. Msleep time control scale is 10ms. For example, msleep (2), the actual sleep is more than 10ms. Because the calling thread will sleep, after sleeping for 10ms, depending on the thread priority, it may still not be executed immediately, so it is generally greater than 10ms.
Problems encountered:
Using mdelay and msleep respectively in Spi delay, the effect is completely different. Using msleep to load the driver's patch is very slow. After replacing mdelay, the speed is faster, but it will consume more cpu resources.
3 I2C communication problems
I2C protocol, 2 bidirectional serial lines, a data line SDA, a clock line SCL.
3.1 I2C bit transfer
Data transmission: SCL is high level, if the SDA line remains stable, then the data bit is transmitted on SDA; if SDA jumps, it means the end or start of the conversation.
3.2 Start and end signals
Start signal: SCL is high, SDA transitions from high to low, and data transmission starts
End signal: SCL is high, SDA transitions from low to high, ending data transmission
3.3 I2C response signal
Master waits for Slave's ACK after sending 8bit data. That is, at the ninth clock, if ACK is sent from I2C, SDA will be pulled low. If there is no ACK, SDA will be set high, which will cause the Master to have a RESTART or STOP process, as shown below:
3.4 I2C write register
1. Master initiates START
2. Master sends I2C addr (7bit) and w operation 0 (1bit), waits for ACK
3. Slave sends ACK
4. Master sends reg addr (8bit), waits for ACK
5. Slave sends ACK
6. Master sends data (8bit), that is, the data to be written in the register, and waits for ACK
7. Slave sends ACK
8. Steps 6 and 7 can be repeated multiple times, that is, write multiple registers sequentially
9. Master initiates STOP
3.5 I2C read register
1. Master sends I2C addr (7bit) and w operation 1 (1bit), waits for ACK
2. Slave sends ACK
3. Master sends reg addr (8bit), waits for ACK
4. Slave sends ACK
5. Master initiates START
6. Master sends I2C addr (7bit) and r operation 1 (1bit), waiting for ACK
7. Slave sends ACK
8. Slave sends data (8bit), which is the value in the register
9. Master sends ACK
10. Steps 8 and 8 9 steps can be repeated many times, that is, read multiple registers sequentially
the master device writes the NAU8810 codec through I2C, it finds that the written value is different from the read value. Write 0x15D to the register, the oscilloscope capture is as follows, as shown in Figure 3-5-1:
The read value register is as follows:
Read general diagram is shown in Figure 3-5-2
Read exploded diagram 3-5-3
The read value is 0x101 , Later, it was found that the I2C write data was not processed according to the chip's protocol. The above is a general protocol, but different chip manufacturers may be different. For example, nau8810 chip:
Nau8810 I2C write reg protocol is as follows:
Note: The data here is 9 bits and the register has only 7 bits. The highest bit of the data is placed in the control Register Address for transmission. Found this and solved the problem.
4 Timer use There is a problem during
debugging : the upper layer sets the handshake tone to generate ACK, and the waveform requirements are as follows:
first generate a 1400Hz tone for 100ms, then stop for 100ms, and then generate a 2300Hz tone for 100ms. The difficulty of the problem is that the time interval between the tone tone at 1400Hz and the tone tone at 2300Hz is required to be 100ms, and the deviation is 3% up and down. If the upper layer does this task, the control accuracy will not meet the requirements. Therefore, timer processing is used at the bottom layer, using methods:
1. Register timing A
init_timer();
2. Register task queue B
INIT_WORK();
3. Add timer
Add_timer();
When the timer expires, the function registered with the timer in the soft interrupt will be executed, and the functions in the task queue will be scheduled in this function, and the task queue will complete different required functions.
5 Interrupt upper
and We want the interrupt service routine to execute as quickly as possible, and at the same time want the program to complete as much work as possible, these two goals are obviously contradictory. Based on this contradiction, we divide the interrupt service routine. There are two parts: the top half and the bottom half.
1. The upper part: the execution starts immediately after receiving an interrupt, with strict time limit requirements, such as responding to the hardware device and resetting the hardware, which are all completed when all interrupts are disabled. The interrupt service routine is the top half.
2. The second half: There is no particularly strict time limit, allowing the work to be completed later to be divided into the lower half. Generally speaking, the second half will be executed immediately when the interrupt service routine returns.
The whole process of the interrupt activity is roughly: copy from: http://cache.baiducontent.com/c? ... 2b000179ca&p1=1
1. Interrupt request: Once the interrupt event occurs or the interrupt condition is formed, the interrupt source submits the "application report" ”, and requesting the CPU to temporarily put down the current work and turn it into an interrupt source as a special service
2. Interrupt masking: Although the interrupt source has submitted an “application report”, whether it gets a response from the CPU depends on whether the “application report” It can be sent to the CPU through 2 or 3 "levels" (interrupt masks) (the corresponding interrupt mask bit is equal to 1, which means the level is released; otherwise, the corresponding interrupt mask bit is equal to 0, which means the level is forbidden to pass);
3. Interrupt response: If it is released all the way, after the CPU responds to the interrupt, it records the interrupted work breakpoint (protects the breakpoint address to the stack), and suspends the "no longer accepting other application report cards" (clears the global interrupt flag bit GIE=0 ), jump to the interrupt service routine
4. Protect the site: the original work site may be damaged when dealing with new tasks, so it is necessary to properly protect the work site and working environment;
5. Investigate the interruption source: check which interruption source the "application report" Make targeted services;
6. Interrupt processing: Start targeted interrupt services for the identified interrupt sources;
7. Clear flags: After processing the corresponding tasks, it is necessary to cancel the registration (clear the interrupt flag), In order to avoid repeated responses;
8. Restoring the site: restore the previously protected work site, so as to continue the interrupted work;
9. Interrupt return: retrieve the interrupted work breakpoint (restore from the stack) Breakpoint address), and remove the "no more application report card" (GIE=1), continue to execute the work that was interrupted. In the
interrupt service subroutine:
A. The interrupt program cannot send or receive data to the user space
B , Can not do any operations that may cause dormancy, wait_event, or lock the semaphore
C, can not call the schdule function.
The spi device cannot be read or written in the interrupt, and can be placed in the lower half of the interrupt to do the spi read and write operations.
1. The upper part is required to be as fast as possible to increase the throughput of the system.
2. The lower half generally has processing methods such as soft interrupts, tasklets, and work queues.
6 nau8810 chip pcm data, matters needing attention in si_3217x chip
Problem nau8810 has noise:
problem analysis: the reason for the noise is that there are two data lines in the 4-wire pcm, one dataIn and one dataOut, because the audio module of the central control is not loaded , the hisi master is not configured with an internal codec, and dirty data is directly output to the codec, resulting in noise problems.
Solution: Power off the pcm data input/output module of nau8810 directly.
Problems in si3217x:
1. The problem of generating 2300Hz tone tone.
It is wrong to generate 2300Hz tone according to the software provided by the chip manufacturer, and there is a problem in the software calculation. Subsequently, according to the formula provided in the manual, manually calculate the value that should be configured to the register. The specific algorithm code is described and will not be repeated here.
2. Configure the ram register Configure the ram register in
strict accordance with the method provided in the chip manual. There is a detailed description in the code and will not be repeated here. The other is the configuration of the reg register No. 74. The value given by the technical support is not correct and needs to be modified to the value in the code.
3. Questions of doubts
Regarding the usage of the interrupt registers 17, 18, and 20 reg registers, the existing code is directly inherited from the mtk platform. I have consulted the technical support, but did not explain it clearly. I can understand it later.