Although the object that the application operates on is the virtual memory mapped to the physical memory, the processor directly operates the physical memory. So when an application accesses a virtual address, it must first convert the virtual address into a physical address, and then the processor can resolve the address access request. The address translation work needs to be completed by querying the page table. The address translation needs to segment the virtual address, so that each segment of the virtual address points to the page table as an index, and the page table entry points to the next level of the page table or points to the final physical page.
Address translation is done in Linux using a three-level page table. Using multi-level page tables can save the storage space occupied by address translation. If the three-level page table is used to translate addresses, even on a 64-bit machine, the space occupied is very limited. But if you use static arrays to implement page tables, even on 32-bit machines, changing the array will take up a huge amount of storage space. Linux uses three-level page tables to manage memory for all architectures.
The top-level page table is the Page Global Directory (PGD), which contains an array of type pgd_t, which is equivalent to an unsigned long in most architectures. The entry in PGD points to the entry in the secondary page directory: PMD.
The second-level page table is the intermediate page directory (PMD), which is an array of type pmd_t, where the entry points to the entry in the PTE.
The page table at the last level is referred to as a page table, which contains a pte_t type page table entry, which points to a physical page.
Each process has its own page table, and the pdg field of the memory descriptor points to the global directory of the process. Manipulating and retrieving page tables must use the page_table_lock lock, which is in the memory descriptor of the corresponding process, to prevent race conditions.
Since almost every page access in virtual memory must be parsed to obtain the corresponding address in physical memory, the performance of page table operations is very critical. Unfortunately, searching for physical addresses in memory is limited, so to speed up searching, most architectures implement a translate lookaside buffer (TLB). TLB is used as a hardware cache that maps virtual addresses to physical addresses. When requesting access to a virtual address, the processor will first check whether the virtual address-to-physical address mapping is cached in the TLB. If it is directly hit in the cache, the physical address Return immediately, otherwise you need to search the required physical address through the page table.