In verilog predictions, in order to distinguish them from general statements, these preprocessing commands start with the symbol "`" (located in the upper left corner of the main keyboard, note that this symbol is different from the single quotation mark'). The effective scope of these preprocessing commands is the definition command Afterwards, to the end of this file or to the place where other commands replace the command, verilog HDL provides many precompiled commands:
`accelerate, `autoexpand_vectornets, `celldefine, `default_nettype, `define, `else, `endif, `timescale.等等
In this blog, I intend to introduce the commonly used `define `include `timescale, and the rest can be consulted if necessary.
1. Macro definition `define:
Represents a string with a specified identifier (namely), whose general form is:
`define identifier (macro name) string (macro content)
如： `define signal string
Its function is to specify the identifier signal to replace the string string. When compiling preprocessing, replace the signal in the program after the command with string. This method enables users to replace a long name with a simple name. , and can also replace meaningless numbers and symbols with meaningful names. Therefore, this identifier (name) is called "
macro name
", and the process of replacing the macro name with a string during compilation preprocessing is called "macro expansion". `define is a macro definition command.
example1:
module test;
reg a, b, c, d, e, out ;
`define expression a+b+c+d;
assign out = `expression + e;
.......
endmodule
2, "file includes" handles `include
The so-called file inclusion process is that a source file can include the entire content of another source file, that is, the other file is included in the text, the verilog HDL language provides the `include, command is used to implement the "file inclusion" operation. Its general form is:
`include "filename"
The "file include" command is very useful, which can save the repetitive work of programmers; some commonly used macro definition commands or tasks can be formed into a file, and then the `include command can be used to include these macro definitions into their own writing. The source file is equivalent to the industry standard original to be used.
example2：
(1) File aaa.v
module aaa(a,b,out);
input a,b ;
output out ;
wire out ;
assign out = a^b;
endmodule
(2) File bbb.v
`include "aaa.v"
module bbb(c,d,e,out)
input c,d,e;
output out;
wire out_a;
wire out ;
aaa aaa(
.a(c),
.b(d),
.out(out_a)
);
assign out = e & out_a;
endmodule
3, time scale `timescale
The `timescale command is used to
specify
the time unit and time precision of the module following the command . Use the `timescale command to include modules with different time units in the same design. For example, if a design contains two modules, one module has a time delay in nanoseconds (ns) and the other module has a time delay in picoseconds (ps), the EDA tool can still simulate the design.
The format of the `timescale command is as follows:
`timescale <time unit>/<time precision>
example3：
`timescale 10ns/1ns
module test ;
reg set ;
parameter d=1.55;
initial
begin
#d set =0;
#d set =1;
end
endmodule
In this example, the `timescale command defines the time unit of the module as 10ns and the time precision as 1ns. Therefore, in the module test, all time values should be an integer multiple of 10ns, and the time precision is 1ns. After this rounding operation, the delay time in parameter d is actually 16ns (ie 1.6*10ns). It means that when the simulation time is 16ns, the register set is assigned a value of 0; when the simulation time is 32ns, the register set is assigned a value of 1.
It is worth noting that:
(1) According to the time precision, the value of parameter d is rounded from 1.55 to 1.6.
(2) Because the time unit is 10ns and the time precision is 1ns, the delay time #d as an integer multiple of the time unit is 16ns.