OPTEE Secure startup log analysis

secure  log
//soc_term directory to implement port monitoring
listening on port 54321
q
soc_term: accepted fd 4
soc_term: read fd EOF
soc_term: accepted fd 4

//mmu related operations
core/arch/arm/kernel/generic_entry_a32.S +431  core_init_mmu_map
./core/arch/arm/mm/core_mmu.c
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: VCORE_UNPG_RX_PA type TEE_RAM_RX 0x0e001000 size 0x00056000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: VCORE_UNPG_RW_PA type TEE_RAM_RW 0x0e057000 size 0x001aa000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: CFG_TA_RAM_START type TA_RAM 0x0e300000 size 0x00d00000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: CFG_SHMEM_START type NSEC_SHM 0x81f00000 size 0x00200000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: SECRAM_BASE type IO_SEC 0x0e000000 size 0x00100000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: CONSOLE_UART_BASE type IO_SEC 0x09000000 size 0x00100000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: GICD_BASE type IO_SEC 0x08000000 size 0x00100000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: GICC_BASE type IO_SEC 0x08000000 size 0x00100000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:537: Physical mem map overlaps 0x8000000
DEBUG:   [0x0] TEE-CORE:add_phys_mem:524: PCSC_BASE type IO_SEC 0x09100000 size 0x00100000

DEBUG:   [0x0] TEE-CORE:verify_special_mem_areas:468: NSEC DDR memory [40000000 81f00000]
DEBUG:   [0x0] TEE-CORE:add_va_space:563: type RES_VASPACE size 0x00a00000
DEBUG:   [0x0] TEE-CORE:add_va_space:563: type SHM_VASPACE size 0x02000000
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type TEE_RAM_RX   va 0x0e001000..0x0e056fff pa 0x0e001000..0x0e056fff size 0x00056000 (smallpg)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type TEE_RAM_RW   va 0x0e057000..0x0e200fff pa 0x0e057000..0x0e200fff size 0x001aa000 (smallpg)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type SHM_VASPACE  va 0x0e300000..0x102fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type IO_SEC       va 0x10300000..0x103fffff pa 0x0e000000..0x0e0fffff size 0x00100000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type RES_VASPACE  va 0x10400000..0x10dfffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type TA_RAM       va 0x10e00000..0x11afffff pa 0x0e300000..0x0effffff size 0x00d00000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type NSEC_SHM     va 0x11b00000..0x11cfffff pa 0x81f00000..0x820fffff size 0x00200000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type IO_SEC       va 0x11d00000..0x11dfffff pa 0x08000000..0x080fffff size 0x00100000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type IO_SEC       va 0x11e00000..0x11efffff pa 0x09000000..0x090fffff size 0x00100000 (pgdir)
DEBUG:   [0x0] TEE-CORE:dump_mmap_table:694: type IO_SEC       va 0x11f00000..0x11ffffff pa 0x09100000..0x091fffff size 0x00100000 (pgdir)
DEBUG:   [0x0] TEE-CORE:core_mmu_alloc_l2:249: L2 table used: 1/4
DEBUG:   [0x0] TEE-CORE:core_mmu_alloc_l2:249: L2 table used: 2/4
DEBUG:   [0x0] TEE-CORE:core_mmu_alloc_l2:249: L2 table used: 3/4
//end mmu operator

//related with thread
INFO:    TEE-CORE:
DEBUG:   [0x0] TEE-CORE:init_canaries:169: #Stack canaries for stack_tmp[0] with top at 0xe07e7f8
DEBUG:   [0x0] TEE-CORE:init_canaries:169: watch *0xe07e7fc
DEBUG:   [0x0] TEE-CORE:init_canaries:169: #Stack canaries for stack_tmp[1] with top at 0xe07eef8
DEBUG:   [0x0] TEE-CORE:init_canaries:169: watch *0xe07eefc
DEBUG:   [0x0] TEE-CORE:init_canaries:169: #Stack canaries for stack_tmp[2] with top at 0xe07f5f8
DEBUG:   [0x0] TEE-CORE:init_canaries:169: watch *0xe07f5fc
DEBUG:   [0x0] TEE-CORE:init_canaries:169: #Stack canaries for stack_tmp[3] with top at 0xe07fcf8
DEBUG:   [0x0] TEE-CORE:init_canaries:169: watch *0xe07fcfc
DEBUG:   [0x0] TEE-CORE:init_canaries:170: #Stack canaries for stack_abt[0] with top at 0xe080538
DEBUG:   [0x0] TEE-CORE:init_canaries:170: watch *0xe08053c
DEBUG:   [0x0] TEE-CORE:init_canaries:170: #Stack canaries for stack_abt[1] with top at 0xe080d78
DEBUG:   [0x0] TEE-CORE:init_canaries:170: watch *0xe080d7c
DEBUG:   [0x0] TEE-CORE:init_canaries:170: #Stack canaries for stack_abt[2] with top at 0xe0815b8
DEBUG:   [0x0] TEE-CORE:init_canaries:170: watch *0xe0815bc
DEBUG:   [0x0] TEE-CORE:init_canaries:170: #Stack canaries for stack_abt[3] with top at 0xe081df8
DEBUG:   [0x0] TEE-CORE:init_canaries:170: watch *0xe081dfc
DEBUG:   [0x0] TEE-CORE:init_canaries:172: #Stack canaries for stack_thread[0] with top at 0xe083e38
DEBUG:   [0x0] TEE-CORE:init_canaries:172: watch *0xe083e3c
DEBUG:   [0x0] TEE-CORE:init_canaries:172: #Stack canaries for stack_thread[1] with top at 0xe085e78
DEBUG:   [0x0] TEE-CORE:init_canaries:172: watch *0xe085e7c

//core/arch/arm/kernel/generic_boot.c  init_primary_helper
INFO: TEE-CORE: OP-TEE version: 2.6.0 #1 Sat Jan 27 2018 08:09:08 UTC arm

//./core/arch/arm/kernel/user_ta.c +603   tee_ta_register_ta_store
DEBUG:   [0x0] TEE-CORE:tee_ta_register_ta_store:609: Registering TA store: 'REE' (priority 10)


//core/arch/arm/mm/mobj.c +565
//service_init(mobj_mapped_shm_init);
DEBUG:   [0x0] TEE-CORE:mobj_mapped_shm_init:579: Shared memory address range: e300000, 10300000

// gic driver related
DEBUG:   [0x0] TEE-CORE:gic_it_set_cpu_mask:266: cpu_mask: writing 0xff to 0x11d00828
DEBUG:   [0x0] TEE-CORE:gic_it_set_cpu_mask:270: cpu_mask: 0x0
DEBUG:   [0x0] TEE-CORE:gic_it_set_prio:283: prio: writing 0x1 to 0x11d00428

// core/tee/se/reader/passthru_reader/driver.c  +137 context_init
// core/include/initcall.h #define driver_init(fn)  __define_initcall("3", fn)
DEBUG:   [0x0] TEE-CORE:context_init:101: 0 reader detected

//core/arch/arm/tee/init.c
//core/arch/arm/kernel/generic_boot.c ---> if (init_teecore() != TEE_SUCCESS)
INFO:    TEE-CORE: Initialized
//core/arch/arm/kernel/generic_boot.c  init_primary_helper
DEBUG:   [0x0] TEE-CORE:init_primary_helper:787: Primary CPU switching to normal world boot

//./core/arch/arm/tee/entry_fast.c  	
//static const struct thread_handlers handlers = {
        .std_smc = tee_entry_std,
        .fast_smc = tee_entry_fast,
        .nintr = main_fiq,
#if defined(CFG_WITH_ARM_TRUSTED_FW)
        .cpu_on = cpu_on_handler,
        .cpu_off = pm_do_nothing,
        .cpu_suspend = pm_do_nothing,
        .cpu_resume = pm_do_nothing,
        .system_off = pm_do_nothing,
        .system_reset = pm_do_nothing,
#else
        .cpu_on = pm_panic,
        .cpu_off = pm_panic,
        .cpu_suspend = pm_panic,
        .cpu_resume = pm_panic,
        .system_off = pm_panic,
        .system_reset = pm_panic,
#endif
};

//IMSG("Dynamic shared memory is %sabled", dyn_shm_en ? "en" : "dis");
INFO:    TEE-CORE: Dynamic shared memory is enabled
//The environment where opteeos loads ta is ready to be completed