Experiment 2 Design of Function Adjustable Synthetic Timer

Purpose

Master the use of input, synthesis, simulation and download of experimental tools such as QuartusII

Master the device features and usage methods of the DE2 development version

Master the main methods and techniques of Verilog HDL sequential logic system design

Master and apply the methods and processes of EDA design

Preview requirements

Understand the method and process of QuartusII and other discipline distribution and download

Understand the working characteristics of the input and output display resources of the development board

Understand the methodology and process of board design, development and testing

Experimental requirements

Design an adjustable synthetic timer. Specific functions:

Display hours, minutes, seconds, and provide zero-setting function. Displayed on a seven-segment tube or LCD screen, a 24/12-hour mode switching function can be considered.

The second, minute, and hour can be modified separately, and the two-digit overall modification can be modified or each bit can be modified independently.

Hourly timekeeping function, the whole hour can be represented by a certain form of LED.

Alarm clock function, set a specific time, and display the alarm clock with a specific LED display at the time. Pay attention to the duration of the alarm clock, and you can also refer to the lazy alarm clock mode.

The initial operation is almost similar to Experiment 1. For details, please refer to Experiment 1 link: Quartus Prime Hardware Experiment Development (DE2-115 Board) Experiment 1 Design of CPU Instruction Calculator

It should be noted that in Experiment 2, the values corresponding to the pins need to be replaced . The specific value table is linked as follows:

FPGA Hardware Experiment 2 Function Adjustable Synthesis Timer Design Experiment Design Pin Settings-Dataset Documentation Resources-CSDN Download

Body code:

module shizhong(clkin,key0,hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7,KEY0,KEY1,key17,key16,key15,LEDR,LEDG,in,key14,key13,key12);
input clkin;
input key0,key17,key16,key15,key14,key13,key12;
input[6:1] in;
input KEY0,KEY1;
reg clk=0;
output reg[6:0] hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7;
output reg[7:0] LEDR,LEDG;
reg[7:0] out2,out3,out4,out5,out6,out7; 
reg[7:0] second;
reg[7:0] minute;
reg[7:0] hour;
reg[7:0] second1;
reg[7:0] minute1;
reg[7:0] hour1;
integer N=25000000;
integer i=0;
reg[16:0] naozhong=0;
reg[16:0] s=0;
integer a=86400;

always@(posedge clkin) //分频
begin
if(i==N)
	begin
		i=0;
		clk=~clk;
	end
else i=i+1;
end

always@(posedge clk)
begin
if(key0) s=0; //置零
else 
//计数
begin
//整点报时
if(s%3600==0)
begin 
LEDR=8'b11111111;
end
else
	begin
		LEDR=8'b00000000;
		s=(s+1)%a;
	end
if(key17&&key16==0&&key15==0) //调整小时
	begin
		if(KEY0==0)s=(s+3600)%a;
		else if(KEY1==0)s=(s-3600)%a;
		else s=s%a;
	end
else if(key17==0&&key16&&key15==0)   //调整分钟
	begin
		if(KEY0==0)s=(s+60)%a;
		else if(KEY1==0)s=(s-60)%a;
		else s=s%a;
	end
else if(key17==0&&key16==0&&key15)   //调整秒
	begin
		if(KEY0==0)s=(s+1)%a;
		
		else if(KEY1==0)s=(s-1)%a;
		else s=s%a;
	end
end
end


always@(key17,key16,key15,s)
begin
//闹钟
if(key17==1&&key16==1&&key15==1)
	begin
		naozhong = 0;
		if(key12)naozhong=naozhong+in;
		else if(key13)naozhong=naozhong+in*60;
		else if(key14)naozhong=naozhong+in*3600;
		else naozhong=naozhong;

		second1=naozhong%60;
		minute1=naozhong/60%60;
		hour1=naozhong/3600;
		out7=hour1/10;
		out6=hour1%10;
		out5=minute1/10;
		out4=minute1%10;
		out3=second1/10;
		out2=second1%10;
		hex7=seven(out7);
		hex6=seven(out6);
		hex5=seven(out5);
		hex4=seven(out4);
		hex3=seven(out3);
		hex2=seven(out2);
		hex1=7'b1111111;
		hex0=7'b1111111;
	end
else
	begin
		second=s%60;minute=s/60%60;hour=s/3600;
		out7=hour/10;out6=hour%10;
		out5=minute/10;out4=minute%10;
		out3=second/10;out2=second%10;
		hex7=seven(out7);
		hex6=seven(out6);
		hex5=seven(out5);
		hex4=seven(out4);
		hex3=seven(out3);
		hex2=seven(out2);
		hex1=7'b1111111;
		hex0=7'b1111111;
	if(s==naozhong)LEDG=8'b11111111;
	else LEDG=8'b00000000;
	end

end


function[6:0] seven;
input [7:0] din;
case(din)
	4'h0:seven=7'b1000000;
	4'h1:seven=7'b1111001;
	4'h2:seven=7'b0100100;
	4'h3:seven=7'b0110000;
	4'h4:seven=7'b0011001;
	4'h5:seven=7'b0010010;
	4'h6:seven=7'b0000010;
	4'h7:seven=7'b1111000;
	4'h8:seven=7'b0000000;
	4'h9:seven=7'b0010000;
	default:seven=7'b1111111;
endcase
endfunction
endmodule

hardware test:

reset to zero

control time

Set an alarm clock, the time is up, the green light is on

Quartus Prime Hardware Experiment Development (DE2-115 Board) Experiment 2 Function Adjustable Synthetic Timer Design

Experiment 2 Design of Function Adjustable Synthetic Timer

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