Memory management can be said to be a relatively difficult module to learn, which is why it is more difficult to learn. One is that memory management involves the implementation principle of hardware and complex algorithms of software, and the other is that there are too many wrong explanations about memory management on the Internet. I hope to be able to do a series of memory management, from hardware implementation to underlying memory allocation algorithm, from kernel allocation algorithm to application memory division, to how memory and hard disk interact, etc., and thoroughly understand the entire context framework of memory management. This section mainly explains the hardware principle and paging management.
CPU accesses memory through MMU
Let's look at a picture first:
It can be clearly seen from the figure how the three parts of CPU, MMU and DDR are distributed in hardware. First, when the CPU accesses the memory, it needs to convert the virtual address to the physical address through the MMU, and then access the memory through the bus. After the MMU is turned on, all addresses that the CPU sees are virtual addresses. After the CPU sends the virtual address to the MMU, the MMU will find out what the physical address corresponding to the virtual address is in the page table through the page table, so as to access the external address. DDR (memory stick).
So if you understand how the MMU converts virtual addresses to physical addresses, you also understand how the CPU accesses memory through the MMU.
MMU converts virtual addresses into physical addresses through page tables. The page table is a special data structure that is placed in the page table area of the system space to store the correspondence between logical pages and physical page frames. Each process has its own page table.
The virtual address accessed by the CPU can be divided into: p (page number), which is used as the index of the page table; d (page offset), the address offset within the page. Now we assume that the size of each page is 4KB, and the page table has only one level, then the page table grows as follows (each row of the page table is 32 bits, the first 20 bits represent the page number p, and the last 12 bits represent the page offset d):
The relationship between CPU, virtual address, page table and physical address is as follows:
The page table contains the base address of the physical memory where each page is located. The combination of these base addresses and page offsets forms the physical address, which can be sent to the physical unit.
We found above that if a first-level page table is used, each process needs a 4MB page table ( if the virtual address space is 32 bits (ie 4GB), each page is mapped 4KB, and each page table entry occupies 4B, Then the process needs 1M page table entries (4GB / 4KB = 1M), that is, the page table (each process has one page table) occupies 4MB (1M * 4B = 4MB) of memory space ). However, for most programs, the space used is far from 4GB, so why map the impossible space ? That is to say, the first-level page table covers the entire 4GB virtual address space, but if the page table entry of a first-level page table is not used, there is no need to create the second-level page table corresponding to this page table entry. That is, secondary page tables can be created only when needed. Do a simple calculation, assuming that only 20% of the first-level page table entries are used, then the memory space occupied by the page table is only 0.804MB (1K * 4B + 0.2 * 1K * 1K * 4B = 0.804MB). In addition to creating the second-level page table when needed, you can also transfer this page from disk to memory, only the first-level page table is in memory, only one second-level page table is in memory, and the rest are all in disk. (Although this is very inefficient), then the page table occupies 8KB at this time (1K * 4B + 1 * 1K * 4B = 8KB). Compared with the 0.804MB in the previous step, the occupied space has been reduced many times! All in all, using multi-level page tables can save memory.
A secondary page table is a page table that is sub-paged. Still taking the previous 32-bit system as an example, a logical address is divided into a 20-bit page number and a 12-bit page offset d. Because the page table is to be re-paged, the page number can be divided into a 10-bit page number p1 and a 10-bit page offset p2. Where p1 is used to access the index of the external page table, and p2 is the page offset of the external page table.