Verilog Learning (11) Intensity and Competition of Actual Combat

One: verilog intensity

1: Concept

　　When a line type is driven by multiple, there is a concept of strength; strength is divided into driving strength and charging strength

2: Drive Strength

　　They are supply, strong, pull, weak, and the strength decreases in turn.

3: When designing RTL or gate-level models, only strong drivers (1, 0, x) or drivers (z) that are weaker than weak are used. Drive strength is only used in the following two cases

　　(1) Use a continuous assignment statement to assign a linear value

　　(2) The gate-level output of the primitive logic gate built in Verilog (such as and and bufif1 used in the following examples)

4: The drive strength must appear as a pair (high, low)

5: The grammar of strength is not synthesizable

2: Experiment to observe the competition between the four driving intensities

　　

1: As shown in the figure, it is divided into three modules: counter module, decoder module, tri-state buffer module

2: Counter module

　　Use the behavior-level counters in the previous section (see Verilog combat 10 counters)

3: Decoder module

　　

 4: Buffer module (instantiate the built-in logic gate bufif1)

　　

 5: Top-level design

　　

 6: vcs dump waveform