4. Variables and assignment
4.1. Variables
The probability of variables in the programming language is supported in Makefile, but there is no variable type, which only represents text data;
variable naming rules: variables can contain characters, numbers, and underscores, but cannot contain ":", "#", "=", " ", variable names are case sensitive.
Definition and use of variables:
4.2. Assignment
There are 4 variable assignment methods in Makefile:
4.2.1. Simple assignment (:=)
The general assignment method in programming language is valid only for the current statement, which is equivalent to assignment in C language. Simple assignment is recommended when there are no special requirements.
x := foo
y := $(x)b
x := new
test :
@echo "x => $(x)"
@echo "y => $(y)"Output result:
4.2.2. Recursive assignment (=)
An assignment operation may affect multiple other variables, and all other variables related to the target variable are affected.
x = foo
y = $(x)b
x = new
test :
@echo "x => $(x)"
@echo "y => $(y)"Output result: 
Note: If it is not necessary, please do not use recursive assignment as much as possible. The assignment number here is not equivalent to the assignment number in the C language.
4.2.3. Conditional assignment (?=)
If the variable is not defined, the variable is defined with the value in the assignment symbol, if it is already defined, the assignment has no effect.
x := foo
y := $(x)b
x ?= new
test :
@echo "x => $(x)"
@echo "y => $(y)"Output result:
4.2.4. Append assignment (+=)
A new value is added after the original variable value, and the original variable and the new value are separated by a space
x := foo
y := $(x)b
x += new
test :
@echo "x => $(x)"
@echo "y => $(y)"Output result:
5. Use of predefined variables
There are some predefined variables in Makefile, which are mainly divided into two categories: automatic variables and special variables.
5.1. Automatic variables
$@ The target in the current rule that triggers the command to be executed
$^ All dependencies in the
current rule $< The first dependency in the current rule
The use of an automatic variable:
.PHONY : all first second third
all : first second third
@echo "\$$@ => $@"
@echo "$$^ => $^"
@echo "$$< => $<"
firtst:
second:
third:Output result: 
Note:
1. The "$" symbol has a special meaning in the Makefile. When printing its literal value, it needs to be escaped with $
2. "$@" needs to be escaped with \$
5.2. Special variables
$(MAKE) The file name of the current make interpreter
$(MAKECMDGOALS) The target name specified on the command line, (command line parameters of make)
$(MAKEFILE_LIST) The list of makefile files that make needs to process, note that the file name of the current Makefile always is at the end of the list, and the filenames are separated by spaces.
$(MAKE_VERSION) The version of the current make interpreter
$(CURDIR) The working target of the current make interpreter
$(.VARIABLES) All defined variable names and lists (predefined variables and custom variables)
$(RM) rm -f
usually We will print $(.VARIABLES) to view the custom variables supported by the current operating system, and then compare the make manual (downloadable from the official website: http://www.gnu.org/software/make/manual/make.html), See the meaning of each variable .
.PHONY : all out first second third test
all out :
@echo "$(MAKE)"
@echo "$(MAKECMDGOALS)"
@echo "$(MAKEFILE_LIST)"
first :
@echo "first"
second :
@echo "second"
third :
@echo "third"
test :
@$(MAKE) first
@$(MAKE) second
@$(MAKE) thirdOutput result:
6. Advanced Topics of Variables - On
6.1. Substitution of variable values
6.1.1. Suffix substitution
Use the specified string to replace the suffix in the variable:
Syntax rules: $(var:cc=o) or ${src1:cc=o}
There cannot be any spaces in the replacement expression. Make supports the use of ${} for variables. value
src1 := a.cc b.cc c.cc
obj1 := $(src1:cc=o)
test1 :
@echo "obj1 => $(obj1)"Output result: 
6.1.2. Pattern substitution
of pattern substitution variables, use % to retain the specified characters in the variable value, and replace other characters
Syntax format: $(var:a%b=x%y) or ${src1:a%b =x%y}
src2 := a11b.c a22b.c a33b.c
obj2 := $(src2:a%b.c=x%y)
test2 :
@echo "obj2 => $(obj2)"Output result: 6.1.3. The meaning
of pattern replacement in the rule : match sub-targets from targets through target-patten; then generate dependencies from sub-targets through prereq-patten; and then constitute the completed rule.
src1 := a.cc b.cc c.cc
obj1 := $(src1:cc=o)
test1 :
@echo "obj1 => $(obj1)"
src2 := a11b.c a22b.c a33b.c
obj2 := $(src2:a%b.c=x%y)
test2 :
@echo "obj2 => $(obj2)"Output result:
6.2. Nested references to variables
A variable name can contain references to other variables, essentially using one variable to represent another.
6.3. Command Line Variables
When running make, you can define variables on the command line, and the command line variables override the variables defined in the Makefile by default.
6.4.override keyword
Used to indicate that the variables defined in the Makefile cannot be overridden, and the override keyword is required for variable definition and assignment
6.5.define keyword
It is used to define multi-line variables in Makefile. The definition of multi-line variables starts from the variable name and ends with endef. The override keyword can be used to prevent the variable from being overwritten. The variable defined by define is equivalent to the variable defined using =.
hm := hello makefile
override var := override-test
define foo
I'm fool!
endef
override define cmd
@echo "run cmd ls ..."
@ls
endef
test :
@echo "hm => $(hm)"
@echo "var => $(var)"
@echo "foo => $(foo)"
${cmd}The result of running the makefile directly: the result 
of passing parameters from the command line:
make makefile foo="i am cmd foomake -f makefile.3" var="cmd line var" 
Obviously we changed the value of the foo variable, because the foo variable is not overridden Modified, but cannot change the value of the var variable.
7. Advanced Topics of Variables - Next
7.1. Environment variables
The value of the environment variable can be used in the Makefile. If the defined common variable and the environment variable have the same name, the environment variable will be overwritten. Specify the -e option when running make, and use the environment variable
first. Advantages: environment variables can be used in all files;
disadvantages: Too many environment variables will lead to reduced portability.
The way variables are passed between different Makefiles:
1. Define environment variables directly externally for transmission
2. Use export to define variables for transmission (define temporary environment variables)
3. Use the make command line Variables are passed (recommended)
PATH := path
export var := D.T.Software
new := TDelphi
test :
@echo "PATH => $(PATH)"
@echo "make another file ..."
@$(MAKE) -f makefile.2
@$(MAKE) -f makefile.2 new:=$(new)Contents of makefile.2:
test:
@echo "PATH => $(PATH)" #1.直接在外部定义环境变量进行传递
@echo "var => $(var)" #2.使用export定义变量进行传递(定义临时环境变量)
@echo "new => $(new)" #3.使用make命令行变量进行传递（推荐）Output result:
7.2. Target variables (local variables)
The scope is only within the specified target and associated rules.
target : name <assignment> value
target : voerride name <assignment> value
7.3. Pattern variables (local variables)
The pattern variable is an extension of the target variable, and the scope is only within the matched target and associated rules.
pattrn : name <assignment > value
pattrn : voerride name <assignment > value
var := D.T.Software
new := TDelphi
test : var := test-var # 目标变量
%e : override new := test-new # 模式变量
test : another
@echo "test :"
@echo "var => $(var)"
@echo "new => $(new)"
another :
@echo "another :"
@echo "var => $(var)"
@echo "new => $(new)"
rule :
@echo "rule :"
@echo "var => $(var)"
@echo "new => $(new)"Direct running results: 
make rule running results: