Summary on the usage of generate

Abtract

    The generate statement allows selection of Elaboration-time or repetition of certain statements. These statements can include module instance reference statements, continuous assignment statements, always statements, initial statements, and gate-level instance reference statements, etc. Elaboration time refers to the stage before the simulation starts, when all design blocks have been linked together and hierarchical referencing is done.

Introduction

1.generate syntax

  • Define genvar as a loop variable for generate.
  • The for statement defined in the generate statement must have begin to prepare for the subsequent addition of tags.
  • begin must have a name, that is, it must have a label, because the label will be used as the instance name of the generate loop.
  • The main types that can be used in the generate statement are:
    • ü module
    • ü UDP (User Defined Primitive)
    • ü Gate-level primitives
    • ü Continuous assignment statement
    • ü initial or always statement
  • The basic structure is as follows:

genvar loop variable name;

generate

    // generate loop statement

    // generate conditional statement

    // generate branch statement

    // nested generate statement

endgenerate

    The following will give some examples of commonly used situations for generate.

2. generate-loop loop statement

 

3.generate-conditional conditional statement

    Generate allows conditional selection of statements, that is, adding the conditional selection to the for loop in generate, and only instantiates the corresponding statement or module when the condition is true.

 

4.generate-case branch statement

    The generate-case branch statement is similar to the generate-conditional statement, except that the original branch statement is replaced by a case statement.

 

Conclusion

    Genvar and generate are only available in Verilog 2001. They are very powerful. They can be used with conditional statements, branch statements, etc. to do some regular instantiation or assignment operations, which are very helpful for improving concise code and reducing human influence.

Reprinted: http://www.cnblogs.com/nanoty/archive/2012/11/13/2768933.html

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