3. Jitter and Signal Integration (Jitter, SI)
Jitter refers to the phenomenon that the edge-hopping moment of a signal deviates from its ideal or expected moment. Noise, non-ideal channels, and non-ideal circuits are all causes of jitter.
Figure 3.1 Clock Jitter
For clock signals, the definition of jitter is different according to different application scenarios. For example, when digital logic calculates timing margin, it is concerned with period jitter. Clock designers prefer phase jitter, because phase jitter can be estimated using the spectrum, and the spectrum can be used to assess the contribution of specific disturbances to the overall phase jitter.
Referring to Figure 3.1, several definitions of jitter are introduced.
l Phase jitter
J phase (n)= t n – n*T. Every period T of an ideal clock is equal and has no jitter. The deviation of a real clock's skipped edges from an ideal clock is called phase jitter.
l Period jitter
J period (n)= (t n - t n-1 ) – T. Period jitter is the deviation of the period of the actual clock from the ideal period. Obviously J period (n) = J phase (n) - J phase (n-1).
l Cycle-to-Cycle jitter
J cycle (n) = (t n - t n-1 ) - (t n-1 - t n-2 ). The deviation of two adjacent cycles before and after is Cycle-Cycle jitter. Obviously J cycle (n) = J period (n) – J period (n-1).
Suppose the maximum phase jitter is +/-J p, and the jitter frequency f jitter = 0.5f clock = 0.5/T, that is,
The phase jitter at time t n-2 is the maximum value +J p , and the phase jitter at time t n-1 is the minimum value -J p
The phase jitter at time t n is the maximum value +J p , and the phase jitter at time t n+1 is the minimum value -J p
Then, the maximum period jitter J period =+/- 2* J p
Then, Cycle-Cycle jitter maximum value J cycle =+/- 4* J p
3.2. Data jitter
Everyone is talking about jitter in the high-speed SerDes space because jitter is directly related to the bit error rate (BER).
An important requirement of the SerDes transmitter is jitter generation—the jitter generated by the transmitter for a specific pattern, rate, and load.
When the signal reaches the receiving end through the channel, it will further amplify the jitter. The frequency components contained in different patterns are different, and the transmission delay of the channel to different frequency components is also different (non-linear phase). Produces deterministic jitter associated with the data pattern. Reflections from impedance discontinuities, crosstalk from adjacent signals, and noise can all cause data jitter.
An important indicator of the SerDes receiver is the jitter tolerance (Jitter Tolerance) - the jitter size that the SerDes receiver can tolerate for a specific code pattern and bit error rate requirement (BER<10 -12 ). When evaluating jitter, graphical means such as eye-diagram, bathtub curve, jitter distribution histogram (PDF), and jitter spectrum are used.
It should be noted that when talking about the data jitter of high-speed SerDes (Tj, Rj, Dj etc.), low-frequency jitter is not included. This is because low frequency jitter is considered a wanderer and can be tracked by the CDR without causing bit errors. When measuring data jitter with an oscilloscope (SDA), you can set the CDR loop bandwidth embedded in the oscilloscope, and the jitter data measured by the oscilloscope has filtered out low-frequency jitter.
Jitter is often divided into several categories according to its cause and probability density function. The significance of classifying jitter is that certain types of jitter can be corrected while others cannot. Classically, total jitter Tj (Total Jitter) is classified as deterministic jitter Dj ( deterministic jitter ) and random jitter Rj ( random jitter ). Jitter is measured in UI or ps, and can be RMS, or peak-to-peak.
3.2.1 Dj
Dj is further subdivided,
l DCD(Duty cycle distortion)
Duty Cycle Distortion Jitter. The bias voltage of the positive and negative terminals of the differential signal is inconsistent, or the rising edge and falling edge time are inconsistent, which will lead to duty cycle distortion. Since DCD is related to the data pattern, it is jitter that can be corrected.
l DDJ(Data dependent jitter)
Data pattern-related jitter, also known as intersymbol interference (ISI ) . DDJ is caused by a suboptimal channel. is the jitter that can be corrected by the equalizer.
l Pj(Periodic jitter)
Periodic jitter. Pj is caused by periodic interference sources on the circuit. For example, the switching frequency of the switching power supply, the crosstalk of the clock signal, etc. Although the switching frequency of the power supply is generally within the tracking range of the CDR, the low-order harmonic components may fall outside the loop bandwidth, or in the jitter peaking region. More importantly, the interference of the power supply harmonics to the VCO in the CDR cannot be suppressed. and tracking, so for the CDR based on Ring VCO, it is necessary to use LDO power supply as much as possible. Pj cannot be corrected by the equalizer.
l BUJ(Bounded uncorrelated jitter)
BUJs are caused by sources of interference other than clocks. If the interference source aggressor and victim are asynchronous, the probability distribution of jitter is a bounded Gaussian distribution, which is also called CBGJ ( Correlated Bounded Gaussian Jitter ). BUJ/CBGJ cannot be corrected.
3.2.2 Rj
Rj is caused by the noise of the semiconductor itself. An important feature is that the probability density function of Rj is Gaussian distribution, has no boundary, and has nothing to do with the data pattern. Only under a certain bit error rate constraint can it be considered bounded.
3.2.3 Ie
Mathematically, the probability distribution function of jitter can be approximated as a convolution of a Gaussian distribution and a double-bottom Larke distribution.
The jitter that contributes to the Gaussian distribution is:
n Rj is a Gaussian distribution
n The effect of a large number of Pj superposition is also Gaussian distribution
n part of BUJ is also Gaussian
The jitter that contributes to the double bottom Lacker distribution is:
n DCD is approximated as a double bottom Lacker probability distribution
Convolution of Gaussian distribution and double bottom Larke distribution:
where W is considered as the peak-to-peak value of deterministic jitter, and δ is the mean square error of the Gaussian distribution. Referring to Figure 3.2, it can be seen that as the deterministic jitter W increases, a double peak appears at the top of the probability density distribution curve. In general the top curve reflects the magnitude of deterministic jitter.
Figure 3.2 PDF of Tj with different Dj and Rj
Putting the probability distribution functions of two transition edges (at 0 UI and 1UI) in a UI in one graph is the bathtub curve of jitter . Because of the wide dynamic range of logarithms, the Y coordinate is displayed in logarithmic form. Figure 3.3 shows the bathtub curve with deterministic jitter W=0.05UI and Gaussian jitter variance 0.05UI.
Figure 3.3 Bathtub Curve of Tj with 0.05 Dj peak and 0.05 Rj RMS
The bathtub curve will also mark the corresponding bit error rate BER coordinates. For example, the peak-to-peak jitter of BER=10^-12 in the figure is Tj(pp)=0.373*2 = 0.746 UI. The ratio of the area under the curve to the total area is the bit error rate. For example, in the figure,
The top of the bathtub curve is mainly the contribution of the deterministic jitter Dj . The closer to the bottom, the greater the contribution of Gaussian jitter, and it decays with the slope of the Gaussian curve, so it is often estimated by using the characteristics of the Gaussian distribution. The following table shows the relationship between the Gaussian distribution and the mean square error.
Within the specified BER, the table can quickly estimate the relationship between the mean square error value and the peak-to-peak value. For example, the root mean square of Gaussian jitter is 0.05UI, and the bit error rate is required to be 10^-12 BER. Looking up the table, we can see that Q=7, then the peak-to-peak value of Gaussian jitter is 0.05UI*7*2 = 0.7UI.
As mentioned earlier, W=0.05UI, Rj=0.05UI calculates the total jitter Tj=0.746UI;
the Gaussian jitter estimated by the Gaussian characteristic is 0.7UI.
If 0.75U is calculated by Tj = Rj(0.7UI)+Dj(0.05UI), it is basically the same, and the difference is due to the quantization error of the drawing program.
4. Signal Integration (SI) and Simulation
4.1 Shindo channel
The frequency range of interest for the SerDes channel is 0 Hz to the Nyquist frequency, which is twice the fundamental frequency of the signal. The fundamental frequency of the signal is half the line rate of the signal, which means that the Nyquist frequency of the signal is the line rate. The damage of the channel to the signal includes insertion loss (insertion loss), reflection (reflection), crosstalk (crosstalk) and so on. These impairments can be represented by the S-parameter channel model. The S-parameter can be measured by a Vector Network Analyzer (Vector Network Analyzer). The channel is not a purely resistive network, it also includes capacitive and inductive. In this way, the delays of components in different frequencies are different, resulting in jitter related to the data pattern.
Each discontinuous impedance point on the channel produces a reflection, and depending on the inverse position, the reflected signal is superimposed on the original signal with different phases, increasing or decreasing the amplitude of the signal.
SerDes signals are in differential form and have strong suppression of common mode interference. Crosstalk is introduced if there is a difference in interference on the +/- ends. Usually the external PCB can ensure that the SerDes data and the interference source maintain a sufficient distance, but due to the consideration of economy inside the chip, it is difficult to ensure sufficient isolation distance between the SerDes signal and the interference source, especially a channel's own transmission signal interferes with its own receiving signal .
4.2 Chip Package Package
The encapsulation package is also part of the channel. The channel outside the chip can be measured by the VNA, and the packaged S-parameter is usually provided by the chip manufacturer, and the two can be cascaded during simulation. Due to the short distance of the package package, insertion loss is usually not the main problem, and the main consideration is the impedance matching problem.
4.3 SI Simulation
Signal Integration (SI) simulation can build a simulation platform by cascading the SerDes transmitter SPICE model, the S-parameter model of the package and channel, and the receiver SPICE model, and use simulation tools to make circuits for different excitations under different test conditions. simulation. Evaluate whether the design requirements are met by measuring the eye diagram of the SerDes receiver. You can also measure the receiver's eye diagram to check whether it meets the receiver's eye diagram template or the eye diagram template specified in the protocol. Figure 4.1 shows the eye diagram and mask of a measured 3.125Gbps signal, and also includes bathtub curves and statistics.
Figure 4.1 Rx-end Eye-diagram of A 3.125Gbps SerDes
For high-speed SerDes (>5Gbps), this traditional circuit simulation method can no longer meet the design requirements. First, the excessive intersymbol interference (ISI) causes the receiver's eye diagram to be completely closed, but after equalization by the in-chip DFE, the eye diagram may be fine. Secondly, the speed of circuit simulation (SPICE) is very slow. Even if there is a way to add DFE equalization to the simulation, since DFE simulation requires long enough bits to train, the simulation time of circuit simulation is unacceptable at this time.
The simulation of high-speed SerDes needs to rely on the method of statistical analysis. The method of statistical analysis treats the connection between the transmitter-channel-receiver as a linear system, calculates the system impulse response h(t), adds a noise source to simulate the jitter, and then convolves the impulse response with the excitation to obtain the signal at the receiver. In this way, the manufacturer's proprietary FFE and DFE adaptive algorithms can be added to the simulation.
Statistical analysis (statistical analysis) method can not simulate the nonlinear and time-varying characteristics of the circuit, so high-speed SerDes often need to combine the two to simulate SI. More information on statistical analysis methods can be found here.
5. The end
Some people have said that today's cars are so complicated that although everyone understands every part, no one can understand them all together as a whole car. In recent years, FPGAs have become more and more complex, and the requirements for engineers have become higher and higher. To become a qualified FPGA application engineer, not only must be good at digital circuit design, but also know high-speed SerDes, signal integration SI, DSP algorithm, multi-core CPU, embedded operating system, etc. Behind every technology is a professional field. A person will not be an expert in every field. As long as you learn a little more than others, your value will be highlighted when it is critical. This article mainly introduces the basic structure of SerDes and some knowledge that needs to be mastered to use SerDes well. I hope it will be helpful to your work.