From: http://xilinx.eetrend.com/article/7734
Clock Articles of XDC Constraint Techniques
Xilinx©'s next-generation design suite Vivado introduces a new constraint file XDC, which is quite different from the UCF supported in the previous generation of ISE in many rules and techniques, bringing many additional challenges to users. Xilinx tool experts tell you that it is actually very easy to use XDC well, you only need to master a few core skills, and always keep in mind: the syntax of XDC is actually the Tcl language.
Advantages of
XDC XDC is the abbreviation of Xilinx Design Constraints, but its basic syntax comes from the industry's unified constraint specification SDC (first proposed by Synopsys, hence the name Synopsys Design Constraints). Therefore, the relationship between SDC, XDC and Vivado Tcl is shown in the following figure.
XDC is essentially the Tcl language, but it only supports basic Tcl syntax such as variables, lists, operators, etc. For other complex loops and file I/O syntax, you can source a Tcl file in Vivado. Replenish. (Readers interested in Tcl topics can refer to the author's other article "The Application of Tcl in Vivado") The main differences between XDC and UCF are two points:
1. XDC can be read by the tool as a whole file like UCF, or it can be directly executed as individual commands in the implementation process. This determines that XDC also has the characteristics of Tcl commands, that is, the constraints entered later will override the constraints entered before in the case of conflict (the priority of timing exceptions will be detailed in the next section). In addition, unlike UCF, which is all read and reprocessed, in XDC, the constraint is to read one and execute one, so the order is very important. For example, before setting IO constraints, the corresponding clock must be created first.
2. UCF looks at the problem from the perspective of FPGA, so by default, all clocks are regarded as asynchronous unless they are pre-declared to be synchronous without cross-clock domain timing analysis; XDC is just the opposite, the blood background of the ASIC world. It is determined that all clocks are regarded as fully synchronized by default. In the absence of timing exceptions, the tool will actively analyze each path that crosses the clock domain.
The basic grammar
of XDC The basic grammar of XDC can be divided into three categories: clock constraints, I/O constraints and timing exception constraints. According to the recommendation of the Baseline part of Xilinx's UltraFast design methodology (detailed in UG949), the order of constraining a design can also be carried out according to these three types of constraints. This article will not explain in detail the basic XDC syntax that can be found in the help documentation, but will focus on usage methods and techniques.
Clock Constraints
Clock constraints must be created first. For 7 series FPGAs, the incoming master clock from the port and the GT's output RXCLK/TXCLK must be created by the user using create_clock. The derived clocks are divided into the following two categories:
The output clocks of MMCM/PLL/BUFR can be automatically derived by Vivado without user creation. If the user only wants to change the name of the derived clock, and the other frequencies are automatically deduced by the tool, he only needs to write three options, and the rest can be left unwritten: create_generated_clock [-name arg] [-source args] [-master_clock arg] The tool cannot automatically deduce the case of derived clocks, including frequency dividers built using registers and combinational logic, and must be created by the user using create_generated_clock.
I/O constraints
In the initial stage of the design, I/O constraints can be omitted, allowing the tool to focus on meeting the timing requirements within the FPGA. When the timing requirements are basically met, the I/O constraints are added. I/O constraints in XDC have the following points to note:
Port timing requirements without any I/O constraints are considered infinite.
XDC中的set_input_delay / set_output_delay对应于UCF中OFFSET IN / OFFSET OUT，但视角相反。OFFSET IN / OFFSET OUT是从FPGA内部延时的角度来约束端口时序，set_input_delay / set_output_delay则是从系统角度来约束。
典型的I/O时序，包括系统同步、源同步、SDR和DDR等等，在Vivado图形界面的XDC templates中都有示例。2014.1版后还有一个Timing Constraints Wizard可供使用。
时序例外约束
时序例外约束包括set_max_delay/set_min_delay，set_multicycle_path，set_false_path等，这类约束除了要满足XDC的先后顺序优先级外，还受到自身优先级的限制。一个总的原则就是针对同一条路径，对约束目标描述越具体的优先级越高。不同的时序例外约束以及同一约束中不同条件的优先级如下所示：
举例来说，依次执行如下两条XDC，尽管第二条最后执行，但工具仍然认定第一条约束设定的15为clk1到clk2之间路径的max delay值。
再比如，对图示路径依次进行如下四条时序例外约束，优胜者将是第二条。但如果再加入最后一条约束，false path的优先级最高，会取代之前所有的时序例外约束。
高效的时钟约束
约束最终是为了设计服务，所以要用好XDC就需要深入理解电路结构和设计需求。接下来我们就以常见FPGA设计中的时钟结构来举例，详细阐述XDC的约束技巧。
时序的零起点
用create_clock定义的主时钟的起点即时序的“零起点”，在这之前的上游路径延时都被工具自动忽略。所以主时钟创建在哪个“点”很重要，以下图所示结构来举例，分别于FPGA输入端口和BUFG输出端口创建一个主时钟，在时序报告中体现出的路径延时完全不同，很明显sysclk_bad的报告中缺少了之前一段的延时，时序报告不可信。
时钟定义的先后顺序
时钟的定义也遵从XDC/Tcl的一般优先级，即：在同一个点上，由用户定义的时钟会覆盖工具自动推导的时钟，且后定义的时钟会覆盖先定义的时钟。若要二者并存，必须使用 -add 选项。
上述例子中BUFG的输出端由用户自定义了一个衍生钟clkbufg，这个衍生钟便会覆盖此处原有的sysclk。此外，图示BUFR工作在bypass模式，其输出不会自动创建衍生钟，但在BUFR的输出端定义一个衍生钟clkbufr，并使用-add 和 -master_clock 选项后，这一点上会存在sysclk和clkbufg两个重叠的时钟。如下的Tcl命令验证了我们的推论。
不同于UCF约束，在XDC中，所有的时钟都会被缺省认为是相关的，也就是说，网表中所有存在的时序路径都会被Vivado分析。这也意味着FPGA设计人员必须通过约束告诉工具，哪些路径是无需分析的，哪些时钟域之间是异步的。
如上图所示，两个主时钟ssclkin和sysclk由不同的端口进入FPGA，再经由不同的时钟网络传递，要将它们设成异步时钟，可以使用如下约束：
其中，-include_generated_clocks 表示所有衍生钟自动跟其主时钟一组，从而与其它组的时钟之间为异步关系。不加这个选项则仅仅将时钟关系的约束应用在主时钟层面。
重叠（单点多个）时钟
重叠时钟是指多个时钟共享完全相同的时钟传输网络，例如两个时钟经过一个MUX选择后输出的时钟，在有多种运行模式的设计中很常见。
如下图所示，clk125和clk250是clkcore_buf的两个输入时钟，不约束时钟关系的情况下，Vivado会对图示路径做跨时钟域（重叠时钟之间）分析。这样的时序报告即便没有违例，也是不可信的，因为clk125和clk250不可能同时驱动这条路径上的时序元件。这么做也会增加运行时间，并影响最终的实现效果。
如果clk125和clk250除了通过clkcore_buf后一模一样的扇出外没有驱动其它时序元件，我们要做的仅仅是补齐时钟关系的约束。
在很多情况下，除了共同的扇出，其中一个时钟或两个都还驱动其它的时序元件，此时建议的做法是在clkcore_buf的输出端上创建两个重叠的衍生钟，并将其时钟关系约束为-physically_exclusive 表示不可能同时通过。这样做可以最大化约束覆盖率，也是ISE和UCF中无法做到的。
其它高级约束
时钟的约束是XDC的基础，熟练掌握时钟约束，也是XDC约束技巧的基础。其它高级约束技巧，包括复杂的CDC（Clock Domain Crossing）约束和接口时序（SDR、DDR、系统同步接口和源同步接口）约束等方面还有很多值得注意的地方。
这一系列《XDC约束技巧》文章还会继续就上述所列方向分篇详述，敬请关注作者的后续更新，以及Xilinx 官方网站和中文论坛上的更多技术文章。