content
kind of definition
First look at a few sets of defined types
The first
Define a variable of data1 (reg) and data2 (wire) with a bit width of 8.
reg [7:0] data1;
wire [7:0] data2;Assignment method
If you want to perform assignment and other operations, you can use the always block for assignment, or use the assign statement.
the second
define a one-dimensional array
Define the memory as a one-dimensional array of type reg, any element in the array can be accessed by a subscript. Such an array is defined as follows:
reg [7:0] data [255:0];Among them, [7:0] represents the bit width of each element in the one-dimensional array, and [255:0] after the variable represents not the bit width, but the depth of the created array. That is, the size of the elements in a one-dimensional array, which can also be called the capacity of the array.
Assignment method
You can directly access the subscript of the element in the array. The following code represents the assignment of the number 1 to the first element in the one-dimensional array.
reg [7:0] data [255:0];
data[0] = 1;the third
Define a two-dimensional array, which can also be said to be a kind of vector.
This definition method is relatively rare, because generally the Verilog code does not involve the definition of two-dimensional arrays. This definition method is very similar to the C language. A two-dimensional array with a bit width of 8. This definition method was discovered when I was doing matrix operations. By defining a two-dimensional array in this way, the values in the matrix can be mapped to each space of the two-dimensional array. On the one hand, a matrix can also be viewed as a two-dimensional array.
reg [7:0] data [255:0] [255:0];
Assignment method
Wrong way:
reg [7:0] data [255:0] [255:0];
assign data[0] = 1;Such assignments will report errors: "Referencing label array 'adaptation' is not a valid net lvalue" and "Illegal left-hand side of contiguous assignment".
First, you cannot use assign to assign values of type reg. The assign type is for the wire type, not the reg type. To operate on a reg type, you need statements inside a logical block like an always block.
Correct way:
reg [7:0] b [0:3] [0:3];
initial begin
// using 2D
for (int i=0; i<=3; i++)
for (int j=0; j<=3; j++)
b[i][j] = i*j;
endEven the Verilog standard does not have a strictly defined understanding of what a 2d array is. This is from the standard:
reg[7:0] mema[0:255]; declares a memory memory of 256 8-bit registers. The indices are 0 to 255.
reg arrayb[7:0][0:255]; declares a two-dimensional array of bit register lines
w_array[7:0][5:0]; declares that the line array
2d array is "reg arrayb[7:0][0:255]; because if the range is put before the name, it is a vector.
Using a 2d array to extend a homogeneous structure by using a for-generate statement is rare. In most cases, one-dimensional vector arrays are used, such as data buses for channels, memory, homogeneous outputs for multiple module instances, etc.