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In this issue, we will continue to introduce the structure of the I/O port of the principle of the single-chip microcomputer. In the previous sharing, we have partially explained the structure of the P1 port and the P3 port. In this issue, we will introduce the structure of the P0 port and the P2 port. , their functions are similar but different, they both have two functions, the P0 port can be used as a common I/O port or as an address and data bus for external memory expansion, and the P2 port also has two functions. One is used as an ordinary I/O port, and the other is used as an external expansion memory, which can be used as the upper eight bits of the address bus.
The two structures have similarities. You can look at the structure of the P0 port and the P2 port through a common simulation method. The structure of the P0 port has two functions, both as a common I/O port and as an address and data bus, so it has a multiplexer switch in it to switch whether it is used as an address data bus or as a common I/O port. The output driver of the P0 port is a pull-up FET inside, and the P1 port is used. It is different from the pull-up resistor inside the P3 port. The driving ability of the P0 port is actually stronger than the driving ability of the P1 port and the P3 port, because it is a field effect transistor, and it actually has a driver. The ability to enhance the function, so its driving ability will be stronger than the P1 port and P3 port.
When the P0 port is used as a common I/O port, the output function and input function of the CPU will be the control terminal of 0, which will play two roles, one is to make the multiplexer switch to the bottom, the other is to make the AND gate The closed segment is 0, and the FET is disconnected. When the pin is connected to the P0 port of the microcontroller as a common I/O port, it is in an open-circuit state. To make the external level state correct, an external Pull-up resistor, when the P0 port is used as a common I/O port, a resistor must be added externally.
When the internal bus is written to 1, the internal bus is 1, the Q non-terminal is 0, and the FET is disconnected through the switch, and the level is uncertain. In order to make it in a certain level state, such as a high level, an external Put on the resistor. At this time, it can be at a certain 5V, and a pull-up level is at a certain level. Otherwise, one side is open circuit, and the other side is also disconnected. It does not know what level it is. This is internal The situation when a 1 is written on the bus.
When 0 is written on the internal bus, the D terminal is 0, the other segment is 1, and the FET at the lower end of the multiplexer is turned on through the wire. This place is connected to D, and the external pin presents a low power Flat, although a pull-up resistor is added externally, the pin still shows a low level. When used as a common I/O port, the pin can generate a correct level state, so the general-purpose microcontroller P0 port is used as a common I/O port. When using the /O port, an external pull-up resistor must be added. The pull-up resistor is generally 4.7K, or a 10K pull-up resistor. It can be found that when it is used as a common I/O port, in fact, as long as an external pull-up resistor is added Resistor, its structure is exactly the same as that of P1 port as a function of ordinary I/O port. This is the output function of ordinary I/O port.
As an input function, the same as a common I/O port control terminal is still 0, the switch is still disconnected when it hits the bottom, and the level of the pin comes through the following path, through this path, you can get a correct In the external level state, the FET must be in the cut-off state. To make it cut off, it is necessary to write 1 on the internal bus first to make the FET in the cut-off state. Can really get the level of the external pin, whether the external is high or low, the read is a low level, so it will be read wrong.
At the same time, it also has the function of reading the latch. In addition to this function, there is another function that is used as an address and data bus. When used as an address and data bus, the control signal line should be kept at 1. When external access When the memory is expanded, that is to say, the P0 port is used as the address and data bus time-sharing. When time-sharing multiplexing, this line will automatically become 1, and the internal address and data bus will be written 0 and 1. At this time, the 0 and 1 should also be displayed on the external pins. When the address and data bus are 0, one end of the AND gate is 0, and the output of the AND gate is 0, which will disconnect the FET. The output of the NOT gate is 0 and the output is 1, which will make the FET conduct to be connected to D and present a low level.
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