Opportunities for various chiplets
Entering the post-Moore's Law era, advanced packaging has become a new phenomenon in the semiconductor industry.
In the process of semiconductor chip manufacturing, after the chip is produced from the fab, it must go through the last very critical step before it can become a component with different functions. This step is: packaging and testing. The so-called packaging is to connect the chip to the printed circuit board or other electronic components, so that the signal and current can be transmitted smoothly. The test is to carry out different degrees of testing at each stage of the chip manufacturing process to confirm the reliability and yield of the chip. Both are indispensable and important procedures in the process of wafer fabrication.
At the same time of packaging, in order to achieve higher performance, chip integration has become the top priority of the development of various manufacturers. Previously, due to the limitation of the process of heterogeneous chip integration (Heterogeneous Integration), there were many differences. The integrated yield rate of the integrated chips is also relatively low. In addition, in the past, most of the packaging factories adopted a division of labor mode, so that most of the manufacturing processes are still mainly based on the integration of homogeneous chips. Based on the perfect semiconductor supply chain in Taiwan and the industrial advantages of top wafer foundry, Taiwan's packaging manufacturers have been in the layout of homogeneous chip integration for many years, and it can indeed be said to be quite mature.
The explosive growth of the advanced packaging market
Driven by the continuous improvement of chip performance requirements in the post-Moore's Law era, the supply chain manufacturers of the semiconductor industry are increasing their investment in the advanced packaging field. The report predicts that between 2020 and 26, the advanced packaging market will grow significantly at a strong annual compound growth rate of 7.9%. By 2025, the market revenue will exceed the scale level of 42 billion US dollars, which is about the expected growth of the traditional packaging market. 2.5D/3D stacked IC, Embedded Die (ED) and Fan-Out (FO) are the three fastest growing technology platforms, with compound annual growth. The rates were 21%, 18% and 16% respectively.
Indeed, as the foundry industry gradually moves towards high-end processes, the process becomes more and more sophisticated, especially after entering 7nm, the projects that can be integrated are more diverse than before, including logic circuits (Logic), radio frequency (RF) circuits , MEMS (Micro-Electro-Mechanical), Sensor (Sensor) and other different chips need to be integrated in the same package. It is a matter of course to provide an overall solution for the integration process of heterogeneous chips, which has become the future development trend of the entire semiconductor industry. The
so-called integration process of heterogeneous chips refers to the integration of various chiplets including memory and logic chips etc., are closely grouped together through advanced packaging processes. With the continuous development of advanced manufacturing processes, the original traditional 2D packaging has been unable to meet the relevant needs, and chip manufacturers have gradually turned to 3D ICs, such as WoW (Wafer-on-Wafer), and even CoW (Chip-on-Wafer) and other technology research and development , This new type of 3D stacked wafer process technology brings more development imagination for the integration of heterogeneous chips.
In the past, homogeneous dies were packaged together, but now two or even more electronic components of different properties (such as logic chips, sensors, memory, etc.) are integrated into a single package; or from the layout of the chip To start, use multi-dimensional space design such as 2.5D/3D to stack and integrate different electronic components into one chip to solve space constraints, improve power consumption and performance, and greatly reduce the volume.
Once the number of integrated projects increases, the complexity and difficulty of the related processes will also increase significantly. In order to make the chips lighter, thinner and shorter to meet the requirements of the terminal, the semiconductor industry does face more challenges that require system-on-chip integration. Looking at the related business opportunities of System in Package, all the first-line semiconductor companies, including TSMC, Samsung, and Intel, are also committed to the development of heterogeneous chip integration processes.
From the perspective of the current layout of various manufacturers, from the outsourced packaging and testing foundries (OSATs) to wafer foundries, for the layout of heterogeneous integrated packaging technologies, it is true that they are sharpened and each has its own advantages. The main layout is SIPon Substrate, low-density fan-out wafer-level packaging (FOWLP) and high-density wafer-level packaging, etc. At the same time, there are also packaging and testing plants that lay out 2.5D ICs; wafer foundries are mainly high-density wafer-level layouts Packaging, 2.5D Interposer and 3D IC, etc.
In order to maintain the company's leading position in the industry, TSMC built the "3D Fabric" platform.
In the past, TSMC, which only focused on the foundry business, began to enter the packaging field since 2009. Provide customers with one-stop turnkey services from front-end foundry to back-end packaging and testing, targeting the artificial intelligence (AI) and high-efficiency computing (HPC) markets. Time.
At present, the two major packaging technologies that TSMC has mass-produced are InFO (integrated fan-out packaging) and CoWoS (chip-on-wafer-on-substrate packaging). InFO packaging technology is actually the FOWLP (Fan-Out Wafer level Package) that has not been widely used by related semiconductor manufacturers because the process yield has never been improved. Until TSMC improved it on the basis of FOWLP technology, and proposed InFO technology in 2015, integrating 16nm logic SoC chips and DRAM chips, it was officially recognized by the market. Because this technology can achieve low power consumption, can emphasize heat dissipation, and can meet applications with small size and high bandwidth, it is especially suitable for use in smartphones, tablet computers and IoT chips. Therefore, TSMC officially mass-produced in 2016. It has since been applied to many end products.
Looking back, TSMC successfully mass-produced 2.5D advanced packaging processes, provided customers with a series of InFO wafer-level packaging technologies, and provided CoWoS packaging processes for high-performance computing chips. It can be said that the semiconductor industry has entered the next new stage. generations. Recently, in response to the layout of advanced packaging, TSMC has frequently reported good news to the market in various public occasions. Recently, in the "Semicon Taiwan 2021 Online Forum", TSMC announced that it has integrated advanced packaging related technologies into the "3DFabric" platform. The front-end technology includes system-on-chip (SoIC), and the back-end assembly and test related technologies include InFO and CoWoS series, allowing customers to choose freely.
In response to the current industry situation, Liao Dedui, deputy general manager of TSMC's operations/advanced packaging technology and services, also bluntly stated that as advanced processes move towards more advanced technologies below three nanometers, the system on integrated chips (System on Integrated Chips; SoIC) small chip advanced packaging technology has become an indispensable solution. TSMC uses small chip integration technology to allow 2.5D heterogeneous packaging to improve chip performance. In other words, small chip heterogeneous chip design has become the current Emerging knowledge of the semiconductor market.
In order to speed up the layout of advanced packaging technology for small chips, TSMC is currently actively building an innovative 3D Fabric advanced packaging and testing manufacturing base. By then, the factory will have production lines for advanced testing, SoIC and 2.5D advanced packaging. The fastest SoIC is expected The introduction of the machine, as for the 2.5D advanced packaging plant, is planned to be in place in 2022. TSMC's intentions for the heterogeneous integration of small chips and the active layout of advanced packaging are self-evident.
ASE holds industrial advantages
Of course, ASE, the leading domestic packaging manufacturer, is not too much to give up. With the advantages of years of hard work in the packaging field, ASE has a head start in SiP advanced packaging technology. Indeed, ASE has grown from the earliest traditional nails. She has considerable experience in 2.5D or 3D in rack-mount packaging, QFN (quad flat no-lead), ball grid array packaging, high-level flip chip packaging and fan-out packaging. System-level packaging that can perform heterogeneous integration for customers and provide customers with one-stop service. There are more and more customers from all over the world entrusting heterogeneous integration cases, which will become the growth momentum of the next stage in the future.
Calculate the cost of Chiplets!
Chiplet can be said to be very popular recently, but the chip industry is not a simple competition of who can make it. It needs to promote the industry update through mass production, and consider product yield, packaging yield, various costs, etc. . Under this premise, only chiplet conversion can significantly exceed the traditional soc solution, which can be very well promoted. Specifically counting money. The data are all real and testable, some of them are obtained from their own chip processing and packaging in 2021, and some are obtained through the chiplet industry alliance.
Abstract/Introduction
Multi-chip integration technology is widely regarded by the industry as a continuation of Moore's Law, and cost saving is one of its well-known advantages, but few works can quantitatively demonstrate the cost advantage of multi-chip integrated systems compared to single-chip systems. Based on three typical multi-chip 2.5D integration technologies, a quantitative multi-chip system cost model is established, and a set of analysis methods is proposed. Cost-effectiveness of system-on-a-chip. The article was accepted by Design Automation Conference (DAC) 2022. Feng Yinxiao, a doctoral student at the Interdisciplinary Institute of Tsinghua University, is the first author of the paper, and Assistant Professor Ma Kaisheng of the Interdisciplinary Institute of Tsinghua University is the corresponding author of the paper.
In recent years, industries including AMD, intel and Huawei have launched a large number of multi-chip integrated products, and the economics of multi-chip architecture has gradually become a consensus. In practice, however, the cost advantages of multi-chip systems are not easily realized due to the cost of packaging and the overhead of Die-to-Die interconnect interfaces. Compared with the traditional single-chip system, the cost calculation of the multi-chip integrated system has become more complicated. If the multi-chip architecture is blindly adopted without careful evaluation, it will lead to higher costs. Therefore, a cost model called the "Chiplet Actuary" was developed to provide a refined assessment of the cost-effectiveness of a multi-chip integrated system, answering many of the challenges facing architects:
What package integration to use plan?
How many small chips should the entire system be broken down into?
Should encapsulation be reused across multiple systems?
How to reuse chips?
How to take advantage of heterogeneous integration?
See the end for specific model details and considerations.
Let 's take a look at some conclusions from the cost model above:
1. Not all chips are economically suitable for Chiplet technology.
The 9 histograms in this picture are all RE Cost (recurring engineering cost, which can be understood as the cost of producing a chip without considering one-time investment), the horizontal direction is 14nm, 7nm, 5nm, and the vertical direction is several chiplets package.
Look at a detailed picture, the 7nm in the above picture, 5 chiplets spelled together to enlarge the version. The horizontal axis of the graph is the area, and the vertical axis is the cost per unit area. The four packaging methods are: SoC, MCM packaging, InFO, and 2.5D packaging.
If it is under 200 square millimeters, there is no need to make chiplets. Big chips above 800mm2 are really profitable. This is why chiplets are used for oversized chips today, because it is indeed more suitable economically.
In addition, with the large amount of testing and packaging costs that come with advanced packaging, extremely advanced packaging is very expensive, even several times the cost of silicon. The first problem to be solved is whether it can make larger chips. In the future, as package prices drop, the chiplets route will become more and more profitable.
The cost of MCM and InFO is relatively lower and more cost-effective. It is expected that chips based on basic packaging in advanced packaging will be available earlier.
2. Multi-chip integration has significant advantages under the more advanced technology (such as 5nm). In a single-chip system with an area of 800mm2, the additional cost caused by silicon wafer defects accounts for more than 50% of the total manufacturing cost. For mature processes (14nm), although yield improvements also save up to 35% in cost, the cost advantage of multi-die diminishes due to D2D interface and packaging overhead (MCM: >25%, 2.5D: >50%).
3. Although the manufacturing cost is the main cost to consider, the cost of one-time input is often decisive, especially for products without huge output guarantees. For a single system, there is a high one-time investment cost for each small chip, such as the cost of the mask during tape-out. Therefore, the multi-chip architecture leads to a very high total one-time investment cost (account for 500,000 output). to 36% of the total cost). For 5nm systems, the multi-chip architecture starts to pay off when volumes hit 20 million.
If a single company wants to build a chip by relying on all the small chips developed by itself, it is not cost-effective if there is only one chip. But it does bring advantages such as the combination of high, medium and low-grade chips.
The one-time investment cost can be accompanied by the reuse of small chips, resulting in huge benefits.
Multiplexing: It has been found through many probing experiments that the cost advantages of multi-chip architectures need to be realized by taking full advantage of multiplexing and heterogeneity. The common multi-chip multiplexing architectures are divided into three categories: single-chip multi-system (SCMS), one-center multi-expansion (OCME) and fixed socket multi-combination (FSMC).
1. For the SCMS architecture, due to chip multiplexing, the chip saves a lot of one-time investment costs compared with the single-chip system. The biggest advantage of this multiplexing scheme is that only one chip is required, and it can take effect immediately without manufacturing multiple chips. This architecture is suitable for products of different grades in the same product line.
2. Compared with SCMC, the OCME architecture makes it possible for heterogeneous processes. If the modules that are not sensitive to advanced processes shared by multiple systems are placed on the central silicon wafer of the backward process, huge benefits can be brought. Many include DDR , PCIe and other modules can use this architecture. The concept of Pkg-reused in the data is package reuse. For example, 4 can be placed on one substrate, but only 2 dies are actually placed, and the other two dies are filled with dummy die to solve the problem of heat dissipation and stress. In this way, the package is not maximized, and it is more cost-effective overall.
3. For the FSMC architecture, the reuse possibility is maximized. The more chips are reused, the greater the amortization of the one-time investment cost. When reusability is fully utilized, the amortized upfront investment is negligible. At this point, the huge cost-saving potential of a multi-chip architecture emerges. The cost advantage is not only reflected in the savings of manufacturing costs, but also in the savings of one-time investment costs. Finally, whoever has more die in hand, or whose solution is compatible with more die, can save more cost.
(In the figure k is how many slots there are on the package, and n is how many different dies are in the hand)
Summary
Multi-chip architecture has become the trend of the future. The advantages of a multi-chip architecture are not unconditional and depend on many complex factors. To help chip architects make better decisions on multi-chip architectures, a quantitative model was developed to compare the costs of different options. Models allow designers to verify costs at an early stage. Shows how multi-die architecture benefits from yield improvements, die and package reuse, and heterogeneity:
Multi-die architecture begins to pay off when the cost of silicon defects exceeds the cost of packaging.
• The closer the system is to the molar limit (state-of-the-art process, largest area), the more cost-effective the multi-chip architecture will be.
The cost-effectiveness brought by smaller chip granularity has a marginal effect, and it is not cost-effective to make a single IP into a die.
Whether to reuse the package depends on which of the manufacturing cost and the amortized one-time input cost dominates. When the quantity is small, the packaging should be reused as much as possible; when the quantity is large, the advanced packaging can be independently developed again. This balance point is about 80-1 million per year.
For homogeneous systems with distinct grades, the SCMS scheme has significant cost advantages; for systems that share large-area HUB modules, the OCME scheme is more cost-effective; the FSMC scheme provides the greatest reuse possibility, but the shape of the die , and the number of interfaces on the four sides is very high.
The basic principle is to build more systems with fewer chips, and the cost-effectiveness of chip reuse is more obvious for fragmented and hierarchical needs.
Advanced packaging is not the more advanced the better, the price is too high, and it is several times the cost of silicon, which determines that it will not be used in mass production; the basic version of the advanced packaging can basically meet the architectural requirements in terms of performance, and may be the most First used on a large scale. Improving yield and reducing costs are the top priorities of domestic packaging factories (especially in substrate production). From the perspective of the future, there are nearly ten substrate manufacturers under construction in China, and several advanced packaging plants are under construction. According to the development rhythm of two years of construction and two-year yield ramping, the advanced packaging yield rate will increase in the next three or four years. And the cost will usher in a substantial optimization. Chiplet technology application will usher in a large-scale explosion.
Model Details and Considerations
Chiplet actuary introduced three concepts of module, chip and package, any system can be composed of these three levels. Each Chiplet corresponds to a module, and the D2D interface is reused among multiple Chiplets as a special module, which can be expressed in mathematical language as:
The manufacturing cost of chips can be roughly divided into: (1) wafer cost, (2) loss due to wafer defect, (3) packaging cost, (4) loss due to packaging defect, and (5) cost due to packaging defect Waste of silicon wafers. (1) (2) Both have been fully discussed in previous work, and the (3) (4) (5) costs associated with multi-chip integration and advanced packaging can be expressed as
: rate, y2 is the yield of chip-to-interposer bonding, and y3 is the bond yield of the intermediate interposer to the substrate. Two different packaging process flows, chip-first and chip-last, are considered: 
one-time investment costs (NRE, including software and IP licensing, system design verification, and tape-out costs, etc.) account for a large part of the total cost. Starting with area, a one-time input cost is introduced into the cost model. For any one chip, the one-time investment cost can be estimated as:
Sc is the area of the chip, Sm is the area of the module, and C is a fixed investment independent of the area. If several systems are to be designed, if they all adopt a single-chip architecture, the total one-time investment cost can be estimated as:
If a multi-chip architecture is adopted, the total one-time investment cost can be estimated as:
Sp is the package area, Cp is the fixed investment in the package, and CD2D is the investment in developing the D2D interface. KmSm: NRE cost related to module area, including module front-end design, module front-end verification, etc. KcSc: NRE cost related to chip area, including architecture design, system verification, back-end design, back-end verification, etc. C: NRE costs unrelated to chip and module area, including software authorization, IP authorization, tape-out (mask cost for chip trial production), etc. KpSp: NRE cost related to package area, including package design, etc. Cp: NRE cost independent of package area, including cost of package manufacturing and mold opening. Other expenses, such as equipment fees, site fees, and routine maintenance fees are included in C or KcSc as appropriate. This cost model has been verified on AMD's multi-chip architecture, and in terms of silicon cost, it has achieved results that are basically consistent with AMD's public data. The difference is that AMD doesn't factor in the additional cost of integrating multiple chips in advanced packaging.
How does Chiplet revolutionize the semiconductor IP business model?
With the continuous development of the integrated circuit industry, the division of labor in the industry has been continuously refined. Today, players in the IC design industry can be subdivided into IC design companies, as well as upstream EDA tool suppliers, semiconductor IP suppliers, and design service providers.
With the increasing number of IP and various interface types, this reusability also faces challenges of increased usage complexity and compatibility. Platform-based design in the integrated circuit design industry, that is, application-oriented, pre-integrating various related IPs to form a scalable and extensible functional platform, an upgradeable IP reusability solution, which can quickly achieve product upgrades Iterate to reduce design risk and design cost.
The rise of new applications drives overall industry growth. The technology replacement from personal computers and peripheral products and broadband Internet to smart phones and mobile Internet has made the market prospects and development opportunities of the semiconductor industry more and more broad. At present, the semiconductor industry has entered the next development cycle after personal computers and smartphones. The main force of change comes from the rise of new applications such as the Internet of Things, cloud computing, artificial intelligence, big data and 5G communications.
Chiplet revolutionizes the semiconductor IP business model.
Chiplet is an unpackaged bare chip (die) that can realize specific functions. One of the new technologies. Chiplets of different suppliers, different process nodes, different functions, and even different materials are like building blocks. They are integrated through advanced packaging technologies (such as EMIB, Foveros, Co-EMIB and other packaging technologies promoted by Intel) to form a system-level chip (SoC).
Chiplet has the characteristics of low cost, flexible design and short development cycle.
Chiplets reduce design costs. The cost of chip design increases with the upgrade of the process. Taking the mainstream design of SoCs with the same area of 22nm and 5nm as an example, the design cost of 22nm is about 45 million US dollars, and the design cost of 5nm is as high as more than 400 million US dollars. The cost difference between the two is as high as 8 times. above. In SoC design, analog circuits, high-power I/Os, etc. are not sensitive to the process, and there is no need to use high-end processes. If the functional modules in the SoC are divided into separate Chiplets, the most appropriate process can be selected for the function Minimize die size, improve yield and reduce cost. Chiplet-based SoCs can purchase dies with specific functions to save their own development and verification costs.
Chiplet broadens the downstream market. The terminal shipments of many market segments are not enough to support the higher mask cost of SoCs, so chip design companies will only develop SoCs for markets with larger downstream shipments (such as smartphones) or higher value. Chiplet-based design enables chip designers to develop high-performance solutions at a lower cost for moderately sized markets (automotive/server, etc.) by selecting mature die to design SoCs.
Chiplets shorten the SoC development cycle. Compared with developing an SoC from scratch, Chiplet can significantly shorten the chip development cycle, help design companies to launch products as soon as possible, increase revenue potential, and gain competitive advantage and market share. There are many advantages of using Chiplet, such as IP multiplexing, design flexibility, low-cost customization, etc., attracting more companies to use Chiplet.
As far as the connection between Chiplet and semiconductor IP is concerned, Chiplet can be regarded as a hardware-based product of semiconductor IP after design and process optimization, and business formation has shifted from the software form of semiconductor IP to the hardware form of Chiplet. Before understanding Chiplet, it is necessary to split semiconductor IP:
semiconductor IP can be divided into soft core (SoftIPCore), solid core (FirmIPCore), and hard core (HardIPCore). Soft cores are usually provided in the form of HDL text (a hardware description language) and do not contain physical information. Users can design them and combine them with other IP cores, so they have high flexibility and are currently the most widely used form of IP. ;Solid core is the addition of layout planning on the basis of soft core; Hard core is provided externally in the form of layout + process file, the layout and process have been fixed, users can use it directly, but cannot modify it, the flexibility is relatively poor . Chiplet can be understood as the embodiment of hard core in the form of silicon chips.
Chiplet has evolved into an IP supplier, an IP supplier with chip design capabilities (not every IP supplier has chip design capabilities), expanding business flexibility and development space. With the continuous development of integrated circuit technology, the complexity of chip design continues to increase. The implementation of Chiplet opens a new reuse mode of IP, that is, IP reuse at the silicon level. IPs with different functions, such as CPU, memory, analog interface, etc., can flexibly choose different processes for production, which can flexibly balance computing performance and cost, and realize the optimal configuration of functional modules without being limited by the fab process.
At present, Chiplet has a small number of commercial applications, attracting international chip manufacturers such as Intel and AMD to invest in related research and development, and is expected to develop into a new chip ecosystem when the current SoC encounters process nodes and cost bottlenecks. According to market research firm Omdia (formerly IHS), the chiplet market will reach $5.8 billion in 2024 and $57 billion by 2035.
Chipet's future is full of opportunities but also challenges, and IP suppliers with chip design capabilities have a better chance to stand out. At the technical level, the challenges Chiplet faces mainly come from several aspects: connection standards, package inspection, software cooperation, and so on.
Connection standards: When users use Chiplets from different suppliers, there needs to be a unified standard to connect dies of different processes/materials to form a system. At present, there are many interface standards, such as OpenCAPI, Gen Z, CCIX, CXL and so on. The standards promoted by various manufacturers are also different. AMD, ARM, Xilinx and other manufacturers support CCIX. Xilinx launched the first chip using the CCIX interface in 2018. Intel supports CXL and provides its leading AIB for free. Standard IP license.
In terms of packaging inspection: According to the bandwidth that needs to be supported between chips, different packaging technologies can be selected. When choosing packaging technologies, cost and connection performance need to be comprehensively considered; Testing is more difficult than testing a complete chip; when testing some chiplets that do not have independent functions, the testing procedure is more complicated.
Software coordination and other aspects: The design and manufacture of Chiplets requires EDA software to provide full support from architecture to implementation to physical design. In addition, the management and invocation of each Chiplet requires unified standards in the industry.
At the business model level, Chiplet will innovate the traditional model of semiconductor IP. The IP supplier mainly provides RTL, the customer pays the license fee after selection, and pays the royalty fee when the designed chip is shipped. The risk borne by the IP supplier is relatively small; when the IP supplier converts the software form IP to the hardware form Chiplet , License and Royalty revenue will be unified into Chiplet revenue, and the time lag between the two revenue will disappear, which is beneficial to the release of revenue/profit of semiconductor IP companies.
At the same time, Chiplet has put forward higher requirements for semiconductor IP suppliers. It not only needs to have the design ability of advanced process, but also needs to have a multi-category IP layout to form a platform operation. VeriSilicon is one of the few manufacturers that can meet the development needs of Chiplet.
Reference link
https://mp.weixin.qq.com/s/baQoJ4ZrPsBEcXGRRLv-4Q
https://mp.weixin.qq.com/s/f17e2AKGV1H_hS0iMDkCpA
https://mp.weixin.qq.com/s/n_U56ZEkP5nb9VLfNrnwXA