2020.10.8 Thursday
1. When doing LVS, an interrupt error occurred.
Solution:
First check whether each component and port terminal correspond well. If this is ok, then look at the file correspondence. Re-create the new schematic and layout files and correspond to the components in them. At the same time, the names of the two files should also correspond to "schematic" and "layout". If there are other names, the software can't find how to correspond.
2. When the layout and schematic are corresponding to the components, the terminal is only in the schematic, and the terminal is not displayed in the layout. How to add a terminal to the layout?
Solution:
Add a pin to the layout, not only the name label, but also the pin
pin① In the layout window, click "create"->"Pin", enter the pin name, and draw a rectangular box at the corresponding position as the pin pin
②Q the pin pin just drawn, modify its matel attribute (note: pin type)
③"L" increase its pin name label
2020.10.12 Monday
I saw a collection of common errors about LVS verification
https://wenku.baidu.com/view/25833421af45b307e87197ee.html
3. The component imported from schematic to layout, when running LVS verification, reported L does not correspond to the problem.
I checked the schematic and layout parameters of the component at this time, as follows
It’s not bad. I re-imported it again, and it’s still the same. Since the error reported that the L of the layout is small, I changed the Segment length (M) of the component in the layout from the original 11.88u to the schematic which is more accurate. 11.885u, LVS passed. Surprised, there is such an operation~
4. Today I encountered the first problem again (1)
When doing the LVS test, schematic and layout can not correspond, use (1) to check the correspondence between components and ports and re-establish a new cell (schematic and layout), still not resolved.
I recalled what I just changed. I changed the schematic of the sub-component (the lower 2 layer of components), and then I re-"i" the changed symbol from the sub-component (the lower 1 layer) and the schematic of this layer, and then Save with "ctrl+x", reload the corresponding layout, and connect.
2020.11.18 Wed.
5, IO port was added to the layout, it has not passed the LVS verification, and the following error is reported:
Solution:
Because the IO ground and the ground of my design part are two grounds, so in the layout, use The psub2 layer frames the part of my design for isolation
2020.12.1 Tuesday
6. Some experiences for drawing layouts:
① When using the copy "C", move "M" and mouse drag in a small field of view, you must be cautious. You may accidentally copy or translate a large area of the layout. Cause a lot of DRC errors.
②. When only a certain layer or a few layers are displayed, be careful to use the frame selection and copy "C", delete and other functions, you may accidentally move things in other invisible layers or Delete it, causing an error.
③,
7. Running LVS and running ERC by the way, reported the following warning: I
found several useful answers on the Internet:
http://bbs.eetop.cn/thread-616968-1-1.html
http://bbs.eetop .cn/thread-334166-1-1.html
http://www.edatop.com/mwrf/270693.html
That is to say, there is no related power and ground naming in the LVS identification file, I checked our technology The LVS identification names are as follows:
2020.12.1 Tuesday
8. Small experience when drawing the layout:
① You cannot enter the lower layer to modify the layout separately. It is better to modify the layout from the top "x" layer by layer, so as to avoid short-circuiting with the upper layer.
② If two people When connecting to a layout, you must communicate with the latest cell in time. It is best not to move the origin of the layout, as this will cause unnecessary trouble. It is best to give all editing rights to one person.
9. The tape-out is composed of several designs into one area, so the density DN problem in DRC needs to be solved when tape-out at the top. Some components used have their own DMEXCL layer for self-protection, and the purpose is to automatically generate dummy At this time, the circled area of the layer will not be filled with dummy and will be avoided. At this time, in order to pass the density detection, we need to manually animate the small dummy square corresponding to the metal layer.
Take the M9 density failure as an example, first open the DNW layer, and fill the 3u*3u square M9 (dm) layer in the DNW box with the actual density problem. M9 (dm) is between each other, M9 (dm) and M9 ( The spacing between drw) needs to be greater than 3um.
Experience: If you use copy, drag or delete operations, you must be very careful, because if you select the frame, there may be other scattered structures on the frame. My experience is to click and select the M9 (dm) small boxes one by one to copy, delete, and move operating. Need patience and meticulousness~